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1. 发明授权

US06658469B1 Method and system for switching between network transport providers 失效
标题翻译：网络传输提供商之间切换的方法和系统
公开(公告)号：US06658469B1
公开(公告)日：2003-12-02
申请号：US09453781
申请日：1999-12-03
申请人： Michael T. Massa , Alessandro Forin , Vadim Eydelman , Timothy M. Morre , Khawar M. Zuberi
发明人： Michael T. Massa , Alessandro Forin , Vadim Eydelman , Timothy M. Morre , Khawar M. Zuberi
IPC分类号： G06F15173
CPC分类号： H04L47/10 , G06F9/54 , H04L47/30 , H04L47/39
摘要： A method and system for directing data transfers between applications and devices residing on different computers or devices using a transport provider switch to determine whether to use a primary transport provider or one of a plurality of alternative transport providers. When an application or device requests to transfer data with another application or device, the transport provider switch detects whether the applications and devices are served by an alternative transport provider and, if so, directs that alternative transport provider to transfer the data. To improve data transfer performance, the switch employs an adaptive protocol that adapts the way data is transferred by observing when an application that is receiving data posts a receive buffer and detects the receive buffer's size. Based upon the application's or device's behavior, the switch transfers the data in a mode that is best suited for the application. A credit-based sequencing method is used to coordinate message transfers.
摘要翻译：一种用于在驻留在不同计算机或设备上的应用和设备之间使用传输提供商交换机来引导数据传输的方法和系统，以确定是使用主要传输提供商还是使用多个替代传输提供者中的一个。当应用或设备请求与其他应用或设备传输数据时，传输提供商交换机检测应用和设备是否由替代传输提供商服务，如果是，则指示该替代传输提供商传送数据。为了提高数据传输性能，交换机采用自适应协议，通过观察正在接收数据的应用程序发布接收缓冲区并检测接收缓冲区的大小来适应数据传输的方式。根据应用程序或设备的行为，交换机以最适合应用程序的模式传输数据。基于信用的排序方法用于协调消息传送。

2. 发明授权

US06981051B2 Adaptive flow control protocol 有权
标题翻译：自适应流控制协议
公开(公告)号：US06981051B2
公开(公告)日：2005-12-27
申请号：US09844153
申请日：2001-04-27
申请人： Vadim Eydelman , Khawar M. Zuberi , Michael T. Massa , Alessandro Forin
发明人： Vadim Eydelman , Khawar M. Zuberi , Michael T. Massa , Alessandro Forin
IPC分类号： G06F9/46 , H04L12/56 , G06F15/16
CPC分类号： H04L47/10 , G06F9/54 , H04L47/30 , H04L47/39
摘要： A method and system for directing data transfers between applications and devices residing on different computers or devices using an adaptive flow control protocol has been described. When an application or device requests to transfer data with another application or device, adaptive flow control protocol adapts the way data is transferred by observing when an application that is receiving data posts a receive buffer and detects the receive buffer's size. Based upon the application's or device's behavior, the adaptive flow control protocol transfers the data in a mode that is best suited for the application.
摘要翻译：已经描述了用于使用自适应流控制协议在驻留在不同计算机或设备上的应用和设备之间引导数据传输的方法和系统。当应用程序或设备请求与其他应用程序或设备传输数据时，自适应流控制协议通过观察正在接收数据的应用程序何时发布接收缓冲区并检测接收缓冲区的大小来调整数据传输的方式。基于应用或设备的行为，自适应流控制协议以最适合于应用的模式传输数据。

3. 发明申请

US20130179377A1 DECISION TREE COMPUTATION IN HARDWARE 有权
标题翻译：硬件中的决策树计算
公开(公告)号：US20130179377A1
公开(公告)日：2013-07-11
申请号：US13344473
申请日：2012-01-05
申请人： Jason Oberg , Ken Eguro , Victor Tirva , Padma Parthasarathy , Susan Carrie , Alessandro Forin , Jonathan Chow
发明人： Jason Oberg , Ken Eguro , Victor Tirva , Padma Parthasarathy , Susan Carrie , Alessandro Forin , Jonathan Chow
IPC分类号： G06F17/00
CPC分类号： G06K9/00986 , G06K9/6282 , G06N5/04 , G06N99/005
摘要： A computing device for use in decision tree computation is provided. The computing device may include a software program executed by a processor using portions of memory of the computing device, the software program being configured to receive user input from a user input device associated with the computing device, and in response, to perform a decision tree task. The computing device may further include a decision tree computation device implemented in hardware as a logic circuit distinct from the processor, and which is linked to the processor by a communications interface. The decision tree computation device may be configured to receive an instruction to perform a decision tree computation associated with the decision tree task from the software program, process the instruction, and return a result to the software program via the communication interface.
摘要翻译：提供了一种用于决策树计算的计算设备。计算设备可以包括由处理器执行的使用计算设备的存储器的部分的软件程序，该软件程序被配置为从与计算设备相关联的用户输入设备接收用户输入，并且响应于执行决策树任务。计算设备还可以包括在硬件中实现的与处理器不同的逻辑电路并且通过通信接口链接到处理器的决策树计算设备。决策树计算装置可以被配置为从软件程序接收执行与决策树任务相关联的决策树计算的指令，处理指令，并且经由通信接口将结果返回给软件程序。

4. 发明申请

US20130044798A1 Side Channel Communications 审中-公开
标题翻译：侧视频通信
公开(公告)号：US20130044798A1
公开(公告)日：2013-02-21
申请号：US13334054
申请日：2011-12-22
申请人： Kenneth Eguro , Alessandro Forin , Ray A. Bittner, JR. , Ji Sun
发明人： Kenneth Eguro , Alessandro Forin , Ray A. Bittner, JR. , Ji Sun
IPC分类号： H04B17/00
CPC分类号： G06F21/554 , G06F21/86 , G06F2221/2101 , H04L63/1425
摘要： A side channel communications system disclosed herein includes a receiver device with an internal circuitry where the operational speed of the internal circuitry changes in response to an external signal. When the receiver device receives an external signal, the operational speed of the internal circuitry changes. A detector detects the change in the operational speed of the internal circuitry to generate an output value, which is decoded to determine the information communicated by the external signal. In one implementation of the side channel communications system, the external transmitter communicates the external signal in the form of a temperature signal. Alternatively, the external transmitter communicates the external signal in the form of a change in the supply voltage.
摘要翻译：本文公开的侧通道通信系统包括具有内部电路的接收机设备，其中内部电路的操作速度响应于外部信号而改变。当接收机设备接收到外部信号时，内部电路的运行速度发生变化。检测器检测内部电路的操作速度的变化以产生输出值，该输出值被解码以确定由外部信号传送的信息。在侧信道通信系统的一个实施方式中，外部发射机以温度信号的形式来传送外部信号。或者，外部发射机以电源电压变化的形式来传送外部信号。

5. 发明申请

US20130044003A1 Intrusion Detection and Communication 有权
标题翻译：入侵检测与通信
公开(公告)号：US20130044003A1
公开(公告)日：2013-02-21
申请号：US13334057
申请日：2011-12-22
申请人： Kenneth Eguro , Alessandro Forin , Ray A. Bittner, JR. , Ji Sun
发明人： Kenneth Eguro , Alessandro Forin , Ray A. Bittner, JR. , Ji Sun
IPC分类号： G08B21/00 , G01R27/28
CPC分类号： G06F21/554 , G06F21/86 , G06F2221/2101 , H04L63/1425
摘要： An intrusion detection system disclosed herein includes a detector circuit that measures a change in value of impedance of an interconnection circuitry. A decoder coupled to the detector decodes the measured value of the change in the impedance of the interconnection circuitry to determine existence of an abnormal condition. In an example implementation of the intrusion detection system, the change in the value of the impedance of the interconnection circuitry is represented by a change in the phase delay on the interconnection circuitry. An implementation of the intrusion detection circuit terminates communication using the interconnection circuitry upon detection of the abnormal condition. The intrusion detection system is further configured to interpret the abnormal condition as a communication signal to the interconnection circuitry.
摘要翻译：本文公开的入侵检测系统包括检测器电路，其测量互连电路的阻抗值的变化。耦合到检测器的解码器解码互连电路的阻抗的变化的测量值，以确定异常状况的存在。在入侵检测系统的示例实现中，互连电路的阻抗值的变化由互连电路上的相位延迟的变化来表示。入侵检测电路的实现在检测到异常情况时终止使用互连电路的通信。入侵检测系统还被配置为将异常状况解释为互连电路的通信信号。

6. 发明申请

US20090177865A1 Extensible Microcomputer Architecture 有权
标题翻译：可扩展的微机架构
公开(公告)号：US20090177865A1
公开(公告)日：2009-07-09
申请号：US12407016
申请日：2009-03-19
申请人： Richard Neil Pittman , Alessandro Forin , Nathaniel L. Lynch
发明人： Richard Neil Pittman , Alessandro Forin , Nathaniel L. Lynch
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30181 , G06F9/3822 , G06F9/3897 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path when fed the instruction's operational code, or an arbiter and multiplexer may resolve conflicts if multiple instruction decode blocks recognize the same instruction. The execution path may be dynamically reconfigured, activated or deactivated as needed, such as to extend an instruction set, to optimize instructions for a particular application program, to implement a peripheral device, to provide parallel computing, and/or based on power consumption and/or processing power needs. Security may be provided by having the reconfigurable execution path loaded from an extension file that is associated with metadata, including security information.
摘要翻译：描述的是包括至少一个可重构执行路径（例如，通过FPGA或CPLD实现）的微处理器架构。当获取指令时，机制确定可重构执行路径（和/或哪个路径）是否将处理该指令。内容可寻址存储器可以用于在馈送指令的操作代码时确定执行路径，或者如果多个指令解码块识别相同的指令，仲裁器和多路复用器可以解决冲突。可以根据需要动态地重新配置，激活或去激活执行路径，例如扩展指令集，优化特定应用程序的指令，实现外围设备，提供并行计算和/或基于功耗和 /或处理电源需求。可以通过使可重新配置的执行路径从与元数据相关联的扩展文件（包括安全信息）加载来提供安全性。

7. 发明授权

US07543309B2 Efficient linking and loading for late binding and platform retargeting 失效
标题翻译：有效的链接和加载用于晚期绑定和平台重定位
公开(公告)号：US07543309B2
公开(公告)日：2009-06-02
申请号：US10923355
申请日：2004-08-20
申请人： Alessandro Forin , Johannes V. Helander
发明人： Alessandro Forin , Johannes V. Helander
IPC分类号： G06F13/00
CPC分类号： G06F9/44521 , G06F8/41 , G06F9/4411 , G06F9/4413 , G06Q10/10 , G06Q40/00
摘要： Methods of optimizing the loading of a previously linked file into working memory in a computer for executing in a memory sharable with other executables, and converting an image which has been previously linked for executing in an unshared memory into an image optimized for use with virtual memory.
摘要翻译：优化将先前链接的文件加载到计算机中的工作存储器中的方法，用于在与其他可执行文件共享的存储器中执行，以及将先前链接的用于在非共享存储器中执行的图像转换为优化用于虚拟存储器的图像。

8. 发明申请

US20080052711A1 HIGHLY COMPONENTIZED SYSTEM ARCHITECTURE WITH LOADABLE VIRTUAL MEMORY MANAGER 失效
标题翻译：具有可负载虚拟内存管理器的高度组合系统架构
公开(公告)号：US20080052711A1
公开(公告)日：2008-02-28
申请号：US11933198
申请日：2007-10-31
申请人： Alessandro Forin , Johannes Helander
发明人： Alessandro Forin , Johannes Helander
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/44521 , G06F8/41 , G06F9/4411 , G06F9/4413 , G06Q10/10 , G06Q40/00
摘要： The present invention is directed to a loadable virtual memory manager, and generally to a computer operating system capable of supporting application programs running in a computer having a working memory, the computer operating system including a kernel resident in the working memory at run time, and a loadable virtual memory manager resident at link time outside of the working memory and dynamically loadable into the working memory at run time upon demand of one of the application programs. The kernel includes a loader for loading the virtual memory manager into the working memory in response to a demand from one of the application programs. The computer is able to access a storage memory separate from the working memory, the loadable virtual memory manager residing at link time in the storage memory. The loader loads the virtual memory manager from the storage memory to the working memory. The loadable virtual memory manager is removable from the working memory upon lack of demand therefor by the application programs.
摘要翻译：本发明涉及一种可加载的虚拟存储器管理器，并且通常涉及能够支持在具有工作存储器的计算机中运行的应用程序的计算机操作系统，该计算机操作系统包括在运行时驻留在工作存储器中的内核，以及一个可加载的虚拟存储器管理器驻留在工作存储器之外的链接时间，并且在应用程序之一的需要时在运行时可动态地加载到工作存储器中。内核包括用于响应于来自应用程序之一的需求将虚拟内存管理器加载到工作存储器中的加载器。计算机能够访问与工作存储器分开的存储存储器，即存储在存储器中的链接时驻留的可加载虚拟存储器管理器。加载器将虚拟内存管理器从存储器加载到工作内存。由于应用程序的需求不足，可加载的虚拟内存管理器可从工作内存中移除。

9. 发明授权

US07246182B2 Non-blocking concurrent queues with direct node access by threads 有权
标题翻译：线程直接节点访问的非阻塞并发队列
公开(公告)号：US07246182B2
公开(公告)日：2007-07-17
申请号：US10966748
申请日：2004-10-15
申请人： Alessandro Forin , Andrew Raffman
发明人： Alessandro Forin , Andrew Raffman
IPC分类号： G06F13/10 , G06F12/00
CPC分类号： G06F5/065 , G06F2205/064 , G06F2205/106
摘要： Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue and dequeue nodes that it may choose. The prior art merely provided access to the values stored in the node. In order to avoid anomalies, the queue is never allowed to become empty by requiring the presence of at least a dummy node in the queue. The ABA problem is solved by requiring that the next pointer of the tail node in each queue point to a “magic number” unique to the particular queue, such as the pointer to the queue head or the address of the queue head, for example. This obviates any need to maintain a separate count for each node.
摘要翻译：使用原子比较和交换（CAS）操作同时维护多个非阻塞FIFO队列。根据本发明，每个队列提供对存储在其中的节点对应用或线程的直接访问，使得每个线程可以将其可选择的节点排队并出队。现有技术仅提供对存储在节点中的值的访问。为了避免异常，通过要求队列中至少存在一个虚拟节点，不允许该队列变空。 ABA问题是通过要求每个队列中的尾部节点的下一个指针指向特定队列所特有的“魔术数”，例如指向队列头的指针或队列头的地址。这不需要为每个节点维护一个单独的计数。

10. 发明授权

US06360220B1 Lock-free methods and systems for accessing and storing information in an indexed computer data structure having modifiable entries 有权
标题翻译：用于在具有可修改条目的索引计算机数据结构中访问和存储信息的无锁方法和系统
公开(公告)号：US06360220B1
公开(公告)日：2002-03-19
申请号：US09223968
申请日：1998-12-31
申请人： Alessandro Forin
发明人： Alessandro Forin
IPC分类号： G06F1730
CPC分类号： G06F17/30949 , G06F9/526 , Y10S707/99938 , Y10S707/99952
摘要： Lock-free methods and systems for accessing information in an indexed computer data structure may include a lookup procedure, an insertion procedure, a removal and replacement procedure, and a release procedure. Each of these procedures accesses entries in an indexed computer data structure, such as a hash table, to access and store information. Each entry in the indexed computer data structure may include an in-use counter to indicate when the entry is in use by one or more threads. The in-use counter permits multiple threads or processes to concurrently access an entry without locks.
摘要翻译：用于访问索引计算机数据结构中的信息的无锁方法和系统可以包括查找过程，插入过程，移除和替换过程以及释放过程。这些过程中的每一个访问索引计算机数据结构中的条目，例如哈希表，以访问和存储信息。索引计算机数据结构中的每个条目可以包括用于指示该条目何时被一个或多个线程使用的用途计数器。使用中的计数器允许多个线程或进程同时访问没有锁的条目。

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