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1. 发明授权

US06543003B1 Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor 失效
标题翻译：用于在无序微处理器中进行多级挂机恢复的方法和装置
公开(公告)号：US06543003B1
公开(公告)日：2003-04-01
申请号：US09436106
申请日：1999-11-08
申请人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , Larry Scott Leitner , Kevin Franklin Reick
发明人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , Larry Scott Leitner , Kevin Franklin Reick
IPC分类号： G06F1100
CPC分类号： G06F9/3885 , G06F9/3861 , G06F11/0757 , G06F11/1405
摘要： A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.
摘要翻译：一种用于在具有多个执行单元的处理器中从挂起状态恢复的方法和装置。执行监视以检测挂起状况。响应于检测挂起状况，分配给多个执行单元的指令被刷新。

2. 发明授权

US06631463B1 Method and apparatus for patching problematic instructions in a microprocessor using software interrupts 有权
标题翻译：使用软件中断在微处理器中修补有问题的指令的方法和装置
公开(公告)号：US06631463B1
公开(公告)日：2003-10-07
申请号：US09436103
申请日：1999-11-08
申请人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , John Anthony Moore , Kevin Franklin Reick , Edward John Silha
发明人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , John Anthony Moore , Kevin Franklin Reick , Edward John Silha
IPC分类号： G06F900
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3802 , G06F9/3861
摘要： A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. A matched instruction may be marked using a match bit that accompanies the instruction through the instruction pipeline. The matched instruction is then replaced with an internal opcode or internal instruction that causes the instruction scheduling unit to take a special software interrupt. The problematic instruction is then patched through the execution of a set of instructions that cause the desired logical operation of the problematic instruction.
摘要翻译：提出了一种用于在数据处理系统中的流水线处理器内修补有问题的指令的方法和装置。获取多个指令，并且将多个指令与至少一个匹配条件进行匹配以生成匹配的指令。匹配条件可以包括匹配指令的操作码，指令的预解码位，指令的类型或其他条件。可以使用伴随指令的匹配位通过指令流水线来标记匹配指令。匹配的指令被替换为内部操作码或内部指令，使指令调度单元进行特殊的软件中断。然后通过执行导致有问题的指令的期望的逻辑操作的一组指令来修补有问题的指令。

3. 发明授权

US06473850B1 System and method for handling instructions occurring after an ISYNC instruction 失效
标题翻译：用于以程序顺序有选择地刷新遵循ISYNC屏障指令的指令的系统
公开(公告)号：US06473850B1
公开(公告)日：2002-10-29
申请号：US09389197
申请日：1999-09-02
申请人： Hoichi Cheong , R. William Hay , James Allan Kahle , Hung Qui Le
发明人： Hoichi Cheong , R. William Hay , James Allan Kahle , Hung Qui Le
IPC分类号： G06F938
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3834
摘要： An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC instruction) unconditionally. The present invention detects the occurrence of any instruction that changes the state of the machine and requires a context synchronizing complete; these instructions are called context-synchronizing-required instructions. When a context-synchronizing-required instruction completes, the present invention sets a flag to note the occurrence of that condition. When an ISYNC instruction completes, the present invention causes a flush and refetches the instruction after the ISYNC if the context-synchronizing-required flag is active. The present invention then resets the context-synchronizing-required flag. If the context-synchronizing-required flag is not active, then the present invention does not generate a flush operation.
摘要翻译： ISYNC指令不会导致无条件地抛出推测分派或获取的指令（在ISYNC指令之后调度或取出的指令）。本发明检测改变机器状态并需要上下文同步完成的任何指令的发生; 这些指令称为上下文同步所需指令。当上下文同步所需指令完成时，本发明设置一个标志以注意该条件的发生。当ISYNC指令完成时，如果上下文同步所需的标志是活动的，本发明引起冲洗并在ISYNC之后重新指定该指令。然后，本发明重置上下文同步所需标志。如果上下文同步所需的标志不是活动的，则本发明不产生刷新操作。

4. 发明授权

US06430678B1 Scoreboard mechanism for serialized string operations utilizing the XER 失效
标题翻译：使用XER的串行字符串操作的记分板机制
公开(公告)号：US06430678B1
公开(公告)日：2002-08-06
申请号：US09363463
申请日：1999-07-29
申请人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
发明人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
IPC分类号： G06F930
CPC分类号： G06F9/30018 , G06F9/3017 , G06F9/325 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.
摘要翻译：通过使用指令排序器单元记分板提供XER记分板功能。如果XER由前一条指令使用，记分板位将被置位。如果获取使用XER的新指令，则生成对XER的虚拟读取以测试记分板位以确定记分板位是否设置。如果执行虚拟读取时记分板位未设置，则X形式的字符串将继续执行。如果在执行虚拟机时设置了记分板位，则流水线停止，直到记分板位被清除，然后执行填充有生成的填充IOP（虚拟或NOP）的X形式字符串。执行访问指令后，记分板位被清除。

5. 发明授权

US06658555B1 Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline 有权
公开(公告)号：US06658555B1
公开(公告)日：2003-12-02
申请号：US09435077
申请日：1999-11-04
申请人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore , David James Shippy , Larry Edward Thatcher
发明人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F930
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3865 , G06F9/3867 , G06F9/3885
摘要： A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline. Preferably, the dispatch unit, in response to the instruction finishing pipeline execution with an exception status, is adapted to use the copy of the instruction to re-issue the instruction to the execution pipeline in a subsequent cycle. In one embodiment, the dispatch unit is adapted to deallocate the copy of the instruction in the pending instruction unit in response to the instruction successfully completing pipeline execution. The pending instruction unit may detect successful completion of the instruction by detecting when the instruction has been pending for a predetermined number of cycles without recording an exception status. In this embodiment, each entry in the pending instruction unit may include a timer field comprising a set of bits wherein the number of bits in the time field equals the predetermined number of cycles. The pending instruction unit may set, in successive cycles, successive bits in the timer field such that successful completion of an instruction is indicated when a last bit in the time field is set. In one embodiment, pending instruction unit includes a set of copies of instructions corresponding to each of a set of instructions pending in the execution pipeline at any given time. In various embodiments, the execution pipeline may comprise a load/store pipeline, a floating point pipeline, or a fixed point pipeline.

6. 发明授权

US06654869B1 Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling 失效
标题翻译：将组标签分配给指令组，其中组标签与该组的单个指令地址一起记录在完成表中，以便于异常处理
公开(公告)号：US06654869B1
公开(公告)日：2003-11-25
申请号：US09428399
申请日：1999-10-28
申请人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore
发明人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore
IPC分类号： G06F500
CPC分类号： G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.
摘要翻译：微处理器包括提取单元，指令分解单元以及调度和完成控制逻辑。提取单元从指令高速缓存中检索一组指令。指令解码单元接收所提取的指令集，并将该组指令组织到指令组中。调度和完成逻辑将组标签分配给指令组，并将组标记记录在完成表的条目中，以跟踪包括指令组的指令的完成状态。调度和控制逻辑可以在对应于每个指令组的完成表条目中记录单个指令地址。优选地，单指令地址是指令组中的第一指令的指令地址。响应于检测到指令组中的指令产生的异常，处理器可以刷新指令组。

7. 发明授权

US06543002B1 Recovery from hang condition in a microprocessor 失效
公开(公告)号：US06543002B1
公开(公告)日：2003-04-01
申请号：US09435066
申请日：1999-11-04
申请人： James Allan Kahle , Hung Qui Le , Kevin F. Reick , David James Shippy , Larry Edward Thatcher
发明人： James Allan Kahle , Hung Qui Le , Kevin F. Reick , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1100
CPC分类号： G06F11/0721 , G06F9/3861 , G06F11/0757 , G06F11/0793 , G06F11/1405
摘要： A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch. The hang recovery unit then asserts a force reject signal to an execution unit to reject all instructions pending in the execution unit's pipeline and a flush signal to the execution unit that results in the processor flushing a set of instructions. The hang recovery unit then negates the force reject, stop completion, and stop dispatch signals to resume processor operation. In one embodiment, the recovery sequence includes entering a relaxed execution mode, such as a debug mode, a serial operation mode, or an in-order mode prior to resuming processor operation. In one embodiment, the processor advances a completion tag upon completing an instruction. In this manner the completion tag indicates the instruction that is next to complete. In one embodiment, the hang recovery sequence includes flushing the processor of an instruction set comprising all instructions with tag information greater than the completion tag. In another embodiment, all instructions with tag information greater than or equal to the completion tag are flushed.

8. 发明授权

US06298436B1 Method and system for performing atomic memory accesses in a processor system 失效
标题翻译：用于在处理器系统中执行原子存储器访问的方法和系统
公开(公告)号：US06298436B1
公开(公告)日：2001-10-02
申请号：US09327644
申请日：1999-06-08
申请人： James Allan Kahle , Hung Qui Le , Larry Edward Thatcher , David James Shippy
发明人： James Allan Kahle , Hung Qui Le , Larry Edward Thatcher , David James Shippy
IPC分类号： G06F9305
CPC分类号： G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3842
摘要： A method and system for atomic memory accesses in a processor system, wherein the processor system is able to issue and execute multiple instructions out of order with respect to a particular program order. A first reservation instruction is speculatively issued to an execution unit of the processor system. Upon issuance, instructions queued for the execution unit which occur after the first reservation instruction in the program order are flushed from the execution unit, in response to detecting any previously executed reservation instructions in the execution unit which occur after the first reservation instruction in the program order. The first reservation instruction is speculatively executed by placing a reservation for a particular data address of the first reservation instruction, in response to completion of instructions queued for the execution unit which occur prior to the first reservation instruction in the program order, such that reservation instructions which are speculatively issued and executed in any order are executed in-order with respect to a partnering conditional store instruction.
摘要翻译：一种用于处理器系统中的原子存储器访问的方法和系统，其中所述处理器系统能够相对于特定程序顺序发出并执行不正常的多个指令。推测性地向处理器系统的执行单元发出第一预约指令。在发行时，响应于在程序中的第一预约指令之后发生的执行单元中检测到任何先前执行的预定指令而从执行单元中刷新在程序顺序中的第一预约指令之后发生的执行单元排队的指令订购。响应于在程序顺序中的第一预约指令之前发生的执行单元排队的指令的完成，通过对第一预约指令的特定数据地址进行预约来推测地执行第一预约指令，使得预约指令相对于合作条件存储指令，以任何顺序被推测地发行和执行的这些被按顺序执行。

9. 发明授权

US08347068B2 Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor 有权
标题翻译：多模式寄存器重命名机制，通过在同时多线程微处理器中的顺序和无序指令处理之间切换时，通过从寄存器重命名缓冲器切换物理寄存器来增加逻辑寄存器
公开(公告)号：US08347068B2
公开(公告)日：2013-01-01
申请号：US11696363
申请日：2007-04-04
申请人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30145 , G06F9/30189 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3885
摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.
摘要翻译：多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

10. 发明授权

US07904661B2 Data stream prefetching in a microprocessor 失效
标题翻译：数据流在微处理器中预取
公开(公告)号：US07904661B2
公开(公告)日：2011-03-08
申请号：US11953637
申请日：2007-12-10
申请人： Eric Jason Fluhr , Bradly George Frey , John Barry Griswell, Jr. , Hung Qui Le , Cathy May , Francis Patrick O'Connell , Edward John Silha , Albert Thomas Williams
发明人： Eric Jason Fluhr , Bradly George Frey , John Barry Griswell, Jr. , Hung Qui Le , Cathy May , Francis Patrick O'Connell , Edward John Silha , Albert Thomas Williams
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.
摘要翻译：在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。数据预取请求被分配与数据流以反映确定的数据流的深度。分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。由处理器执行的指令中的预取控制位控制预取硬件配置。

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