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1. 发明申请

US20130318271A1 CABLE HARNESS SWITCHES 审中-公开
标题翻译：电缆线束开关
公开(公告)号：US20130318271A1
公开(公告)日：2013-11-28
申请号：US13977912
申请日：2011-01-31
申请人： Michael Schlansker , Michael Renne Ty Tan , Nathan Lorenzo Binkert , Dale C. Morris , Wayne V. Sorin
发明人： Michael Schlansker , Michael Renne Ty Tan , Nathan Lorenzo Binkert , Dale C. Morris , Wayne V. Sorin
IPC分类号： G06F13/40
CPC分类号： G06F13/40 , H04L49/40 , H04L49/60
摘要： In one implementation, a cable harness switch includes a plurality of input ports, a first plurality of output ports, a second plurality of input ports, and a circuit switch module. Each input port from the plurality of input ports is configured to be coupled to a network link. Each output port from the first plurality of output ports is configured to be coupled to a network link. Each output port from the second plurality of output ports configured to be coupled to a network switch device. The circuit switch module is operatively coupled to the plurality of input ports, the first plurality of output ports, and the second plurality of output ports to define a network circuit including an input port from the plurality of input ports and an output port from the first plurality of output ports and the second plurality of output ports.
摘要翻译：在一个实施方式中，电缆束开关包括多个输入端口，第一多个输出端口，第二多个输入端口和电路开关模块。来自多个输入端口的每个输入端口被配置为耦合到网络链路。来自第一多个输出端口的每个输出端口被配置为耦合到网络链路。来自第二多个输出端口的每个输出端口被配置为耦合到网络交换设备。电路开关模块可操作地耦合到多个输入端口，第一多个输出端口和第二多个输出端口，以限定包括来自多个输入端口的输入端口的网络电路和来自第一多个输出端口和第二多个输出端口。

2. 发明授权

US08505020B2 Computer workload migration using processor pooling 有权
标题翻译：使用处理器池的计算机工作负载迁移
公开(公告)号：US08505020B2
公开(公告)日：2013-08-06
申请号：US12870835
申请日：2010-08-29
申请人： Christophe de Dinechin , Dale C. Morris , Patrick Knebel , Russ W. Herrell
发明人： Christophe de Dinechin , Dale C. Morris , Patrick Knebel , Russ W. Herrell
IPC分类号： G06F9/46 , G06F15/173 , G06F1/00 , G06F11/00
CPC分类号： G06F9/5088
摘要： An event calling for a migration of a workload from a source processor set of processing units to a target processor set of processing units is detected. Processes of the workload are allocated to a second processor set of processing units so that some workload processes are executed on the source processor set and some workload processes are executed on a second processor set of processor units. Then, some workload processes are allocated to the second processor set so that no workload process is executing on the source processor set and at least some of said processes are executing on the second process set. The second processor set can be the target processor set or an intermediate processor set from which the workload is migrated to the target processor set.
摘要翻译：检测到要求将工作负载从源处理器集合处理单元迁移到处理单元集合的事件。工作负载的处理被分配给处理单元的第二处理器集合，使得在源处理器集上执行一些工作负载过程，并且在第二处理器单元集合上执行一些工作负载过程。然后，一些工作负载过程被分配给第二处理器集，使得在源处理器集上不执行工作负载过程，并且至少一些所述进程在第二进程集上执行。第二处理器集合可以是目标处理器集合或中间处理器集合，工作负载从该集中迁移到目标处理器集合。

3. 发明授权

US08219996B1 Computer processor with fairness monitor 有权
标题翻译：具有公平监视器的计算机处理器
公开(公告)号：US08219996B1
公开(公告)日：2012-07-10
申请号：US11746067
申请日：2007-05-09
申请人： Dale C. Morris
发明人： Dale C. Morris
IPC分类号： G06F9/46 , G06F15/173 , G06F9/30 , G06F13/00
CPC分类号： G06F9/4881
摘要： A computer processor includes a fairness monitor for monitoring allocations of a processor resource to requestors. If unfairness is determined, a resource allocator is biased to offset said unfairness.
摘要翻译：计算机处理器包括用于监视对请求者的处理器资源的分配的公平监视器。如果确定不公平，则资源分配者有偏见以抵消所述不公平性。

4. 发明授权

US07680999B1 Privilege promotion based on check of previous privilege level 失效
标题翻译：基于先前特权级别检查的特权推广
公开(公告)号：US07680999B1
公开(公告)日：2010-03-16
申请号：US09499720
申请日：2000-02-08
申请人： Dale C. Morris , James M. Hull
发明人： Dale C. Morris , James M. Hull
IPC分类号： G06F12/00 , G06F12/14
CPC分类号： G06F9/468 , G06F9/30076
摘要： A secure promotion mechanism promotes a current privilege level of a processor in a computer system. The current privilege level controls application instruction execution in the computer system by controlling accessibility to system resources. An operating system performs a privilege promotion instruction, which is stored in a first page of memory not writeable by an application instructions at a first privilege level. The privilege promotion instruction reads a stored previous privilege level state, compares the read previous privilege level state to the current privilege level, and if the previous privilege level state is equal to or less privileged than the current privilege level, promotes the current privilege level to a second privilege level which is higher than the first privilege level.
摘要翻译：安全促销机制促进计算机系统中处理器的当前特权级别。当前的权限级别通过控制系统资源的可访问性来控制计算机系统中的应用程序指令执行。操作系统执行特权提升指令，该指令被存储在不能由第一特权级别的应用指令写入的存储器的第一页中。特权提升指令读取存储的先前的权限级别状态，将读取的先前权限级别状态与当前权限级别进行比较，并且如果先前的权限级别状态等于或低于当前权限级别的权限，则将当前权限级别提升到第二个权限级别高于第一个权限级别。

5. 发明申请

US20130107879A1 COMPUTER SYSTEM WITH FABRIC MODULES 有权
标题翻译：具有织物模块的计算机系统
公开(公告)号：US20130107879A1
公开(公告)日：2013-05-02
申请号：US13808507
申请日：2010-09-15
申请人： Martin Goldstein , Dale C. Morris , Michael R. Krause
发明人： Martin Goldstein , Dale C. Morris , Michael R. Krause
IPC分类号： H04L12/56
CPC分类号： H05K7/1489 , B23P19/00 , G06F1/181 , H04L49/40 , H05K7/1487 , H05K7/1492
摘要： A chassis is configured to hold at least one horizontal row of node modules and a fabric module. The fabric module can be positioned above or below the row so that it can communicatively couple two or more node modules. Each of the node modules and the fabric modules can be inserted into and removed from the chassis longitudinally.
摘要翻译：机箱被配置为容纳至少一个水平行的节点模块和结构模块。织物模块可以位于行的上方或下方，使得其可以通信地耦合两个或更多个节点模块。节点模块和结构模块中的每一个都可以纵向插入和移出底盘。

6. 发明授权

US07680990B2 Superword memory-access instructions for data processor 失效
标题翻译：数据处理器的超级内存访问指令
公开(公告)号：US07680990B2
公开(公告)日：2010-03-16
申请号：US10449442
申请日：2003-05-30
申请人： Donald C. Soltis , Dale C. Morris , Dean Ahmad Mulla , Achmed Rumi Zahir , Amy Lynn O'Donnell , Allan Douglas Knies
发明人： Donald C. Soltis , Dale C. Morris , Dean Ahmad Mulla , Achmed Rumi Zahir , Amy Lynn O'Donnell , Allan Douglas Knies
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30087 , G06F9/30112 , G06F9/3834
摘要： Atomic sixteen-byte memory accesses are provided in a 64-bit system in which eight of the bytes are stored in a 64-bit general-purpose register and eight of the bytes are stored in a 64-bit special-purpose register. A 16-byte load instruction transfers the low eight bytes to an explicitly specified general-purpose register, while the high eight bytes are transferred to the special-purpose register. Likewise, a 16-byte store instruction transfers data from a general-purpose register and the special-purpose register. Also provided is an 8-byte compare conditioning a 16-byte exchange semaphore instruction that can be used to accelerate algorithms that use multiple processors to simultaneously read and update large databases.
摘要翻译：在64位系统中提供原子十六字节的存储器访问，其中八个字节存储在64位通用寄存器中，八个字节存储在64位专用寄存器中。一个16字节的加载指令将低8个字节传送到明确指定的通用寄存器，而高8个字节传送到专用寄存器。同样，一个16字节的存储指令从通用寄存器和专用寄存器传送数据。还提供了一个8字节比较调节16字节交换信号量指令，可用于加速使用多个处理器同时读取和更新大型数据库的算法。

7. 发明授权

US07340630B2 Multiprocessor system with interactive synchronization of local clocks 有权
标题翻译：具有本地时钟交互式同步的多处理器系统
公开(公告)号：US07340630B2
公开(公告)日：2008-03-04
申请号：US10638696
申请日：2003-08-08
申请人： Dale C. Morris , Jonathan K. Ross
发明人： Dale C. Morris , Jonathan K. Ross
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： G06F1/14 , H04J3/0638
摘要： A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization masters. The present master transmits a “request” time stamp (indicating the time of transmission according to the local clock) to the other (“slave”) processors. Each slave processor responds by returning a “response” time stamp (indicating the time of transmission of the response according to the local slave clock) of its own along with the received request time stamp. The master calculates clock adjustment values from the time of receipt of the responses and the included time stamps. This allows asynchronous clocks to be synchronized so that application time stamps can be validly compared across processors.
摘要翻译：多处理器计算机系统包括多个数据处理器，每个数据处理器具有用于向应用软件提供时间戳的内部时钟。处理器轮流作为同步主机。本主机向另一个（“从”）处理器发送“请求”时间戳（指示根据本地时钟发送的时间）。每个从属处理器通过根据接收到的请求时间戳返回一个“响应”时间戳（指示根据本地从属时钟发送响应的时间）。主人从接收到响应时间和包含的时间戳计算时钟调整值。这允许异步时钟被同步，以便可以在处理器之间有效地比较应用程序时间戳。

8. 发明授权

US07143270B1 System and method for adding an instruction to an instruction set architecture 有权
标题翻译：用于向指令集架构添加指令的系统和方法
公开(公告)号：US07143270B1
公开(公告)日：2006-11-28
申请号：US10769203
申请日：2004-01-30
申请人： Kevin W. Rudd , Allan D. Knies , Dale C. Morris , James M. Hull
发明人： Kevin W. Rudd , Allan D. Knies , Dale C. Morris , James M. Hull
IPC分类号： G06F9/44
CPC分类号： G06F9/30181 , G06F9/30072 , G06F9/30174
摘要： A processor comprising a feature indicator associated with at least one of a first sequence of one or more instructions, a first register, a second register, and an execution core is provided. The execution core is configured to execute a second instruction to cause the first register to be set to a first value using the feature indicator and to cause the second register to be set to a second value using the feature indicator. The execution core is configured to execute the first sequence of one or more instructions to cause a function to be performed in response to the first value in the first register indicating a true condition, and the execution core is configured to execute a second sequence of one or more instructions to cause the function to be performed in response to the second value in the second register indicating the true condition.
摘要翻译：提供了一种包括与一个或多个指令的第一序列，第一寄存器，第二寄存器和执行核心中的至少一个相关联的特征指示符的处理器。执行核心被配置为执行第二指令，以使用特征指示器将第一寄存器设置为第一值，并且使用特征指示器将第二寄存器设置为第二值。执行核心被配置为执行一个或多个指令的第一序列，以使得响应于第一寄存器中指示真实条件的第一值来执行功能，并且执行核心被配置为执行一个第二序列或更多的指令，以响应于指示真实条件的第二寄存器中的第二值来执行功能。

9. 发明授权

US06631460B1 Advanced load address table entry invalidation based on register address wraparound 有权
标题翻译：基于注册地址环绕的高级加载地址表条目无效
公开(公告)号：US06631460B1
公开(公告)日：2003-10-07
申请号：US09559508
申请日：2000-04-27
申请人： Dale C. Morris , William R. Bry , Alan H. Karp , William Chen
发明人： Dale C. Morris , William R. Bry , Alan H. Karp , William Chen
IPC分类号： G06T930
CPC分类号： G06F9/3834 , G06F9/30127 , G06F9/3842
摘要： A computer system includes physical registers holding data for compiled programs and a portion of the physical registers form a register stack which wraps around when full. An N-bit current wraparound count state tracks physical register remapping events which cause the register stack to wraparound or unwrap. An advanced load address table (ALAT) has entries corresponding to load instructions, each entry has at least one memory range field defining a range of memory locations accessed by a corresponding load instruction, a physical register number field corresponding to a physical register accessed in the corresponding load instruction, and an N-bit register wraparound field which corresponds to the N-bit current wraparound count state for the corresponding load instruction. A check instruction accesses the ALAT to determine whether a store instruction and an advanced load instruction, which is scheduled before the store instruction, potentially accessed a common memory location. After the execution of the store instruction, an absence of an entry corresponding to the load instruction in the ALAT indicates that a common memory location may have been accessed by the store and load instructions.
摘要翻译：计算机系统包括保存用于已编译程序的数据的物理寄存器，并且部分物理寄存器形成寄存器堆栈，其在满地时包围。 N位当前环绕计数状态跟踪导致寄存器堆栈环绕或解开的物理寄存器重映射事件。高级加载地址表（ALAT）具有对应于加载指令的条目，每个条目具有至少一个存储器范围字段，其定义由相应的加载指令访问的存储器位置的范围，对应于物理寄存器访问的物理寄存器号字段相应的加载指令和对应于相应加载指令的N位当前环绕计数状态的N位寄存器环绕字段。检查指令访问ALAT以确定在存储指令之前调度的存储指令和高级加载指令是否潜在地访问公共存储器位置。在执行存储指令之后，没有与ALAT中的加载指令相对应的条目指示可以通过存储和加载指令访问公共存储器位置。

10. 发明授权

US5928356A Method and apparatus for selectively controlling groups of registers 失效
标题翻译：用于选择性地控制寄存器组的方法和装置
公开(公告)号：US5928356A
公开(公告)日：1999-07-27
申请号：US947541
申请日：1997-10-11
申请人： Roger A. Golliver , Jerome C. Huck , Dale C. Morris
发明人： Roger A. Golliver , Jerome C. Huck , Dale C. Morris
IPC分类号： G06F9/30 , G06F9/318 , G06F9/46 , G06F9/312
CPC分类号： G06F9/30123 , G06F9/30076 , G06F9/30101 , G06F9/3013 , G06F9/462
摘要： A method and apparatus for controlling groups of registers includes a pluity of registers of the same type logically separated into a plurality of groups and a plurality of indicators corresponding to the plurality of groups of registers, each of the plurality of indicators identifying whether a corresponding group of registers has been modified by a task currently being executed by the processor. A control logic is also included, coupled to the plurality of registers, to selectively control the plurality of registers by group based at least in part on the plurality of indicators.
摘要翻译：用于控制寄存器组的方法和装置包括：逻辑上分成多个组的相同类型的多个寄存器和对应于多组寄存器的多个指示符，多个指示符中的每一个指示符标识相应组的寄存器已由当前由处理器执行的任务修改。还包括耦合到多个寄存器的控制逻辑，以至少部分地基于多个指示符按组选择性地控制多个寄存器。

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