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1. 发明授权

US07143270B1 System and method for adding an instruction to an instruction set architecture 有权
标题翻译：用于向指令集架构添加指令的系统和方法
公开(公告)号：US07143270B1
公开(公告)日：2006-11-28
申请号：US10769203
申请日：2004-01-30
申请人： Kevin W. Rudd , Allan D. Knies , Dale C. Morris , James M. Hull
发明人： Kevin W. Rudd , Allan D. Knies , Dale C. Morris , James M. Hull
IPC分类号： G06F9/44
CPC分类号： G06F9/30181 , G06F9/30072 , G06F9/30174
摘要： A processor comprising a feature indicator associated with at least one of a first sequence of one or more instructions, a first register, a second register, and an execution core is provided. The execution core is configured to execute a second instruction to cause the first register to be set to a first value using the feature indicator and to cause the second register to be set to a second value using the feature indicator. The execution core is configured to execute the first sequence of one or more instructions to cause a function to be performed in response to the first value in the first register indicating a true condition, and the execution core is configured to execute a second sequence of one or more instructions to cause the function to be performed in response to the second value in the second register indicating the true condition.
摘要翻译：提供了一种包括与一个或多个指令的第一序列，第一寄存器，第二寄存器和执行核心中的至少一个相关联的特征指示符的处理器。执行核心被配置为执行第二指令，以使用特征指示器将第一寄存器设置为第一值，并且使用特征指示器将第二寄存器设置为第二值。执行核心被配置为执行一个或多个指令的第一序列，以使得响应于第一寄存器中指示真实条件的第一值来执行功能，并且执行核心被配置为执行一个第二序列或更多的指令，以响应于指示真实条件的第二寄存器中的第二值来执行功能。

2. 发明授权

US09223600B1 In-processor dynamic address redirection table for substituting instruction strings 有权
标题翻译：用于替换指令字符串的处理器内动态地址重定向表
公开(公告)号：US09223600B1
公开(公告)日：2015-12-29
申请号：US11745422
申请日：2007-05-07
申请人： Jonathan K. Ross , Dale C. Morris , James M. Hull
发明人： Jonathan K. Ross , Dale C. Morris , James M. Hull
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/45525
摘要： A data processor includes a redirection dynamic address redirection table (DART) for redirecting instruction fetches from an original memory location with an original address to a target memory location with a target address.
摘要翻译：数据处理器包括重定向动态地址重定向表（DART），用于将具有原始地址的原始存储器位置的指令取出重定向到具有目标地址的目标存储器位置。

3. 发明授权

US06813627B2 Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operands 有权
标题翻译：使用对较小操作数进行操作的原始多媒体操作来执行整数乘法运算的方法和装置
公开(公告)号：US06813627B2
公开(公告)日：2004-11-02
申请号：US09920250
申请日：2001-07-31
申请人： James M. Hull , Dale C. Morris
发明人： James M. Hull , Dale C. Morris
IPC分类号： G06F752
CPC分类号： G06F7/5324 , G06F2207/3828
摘要： Integer multiply operations using data stored in an integer register file are performed using multi-media primitive instructions that operate on smaller operands. The present invention performs a multiply operation on a 32-bit or 64-bit value by performing multiply operations on a series of smaller operands to form partial products, and adding the partial products together. Data manipulation instructions are used to reposition 16-bit segments of the 32-bit operands into positions that allow the multi-media parallel multiply instructions to compute partial products, and the partial products are then added together to form the result. In every embodiment, the present invention achieves better latencies than the prior art method of performing integer multiply operations provided by the IA-64 architecture.
摘要翻译：使用在较小的操作数上操作的多媒体原语指令来执行使用存储在整数寄存器文件中的数据的整数乘法运算。本发明通过对一系列较小的操作数执行乘法运算来形成部分乘积，并且将部分乘积相加在一起，对32位或64位值进行乘法运算。数据操作指令用于将32位操作数的16位段重新定位到允许多媒体并行乘法指令计算部分乘积的位置，然后将部分乘积相加在一起形成结果。在每个实施例中，本发明实现了比由IA-64架构提供的执行整数乘法运算的现有技术方法更好的延迟。

4. 发明授权

US07680999B1 Privilege promotion based on check of previous privilege level 失效
标题翻译：基于先前特权级别检查的特权推广
公开(公告)号：US07680999B1
公开(公告)日：2010-03-16
申请号：US09499720
申请日：2000-02-08
申请人： Dale C. Morris , James M. Hull
发明人： Dale C. Morris , James M. Hull
IPC分类号： G06F12/00 , G06F12/14
CPC分类号： G06F9/468 , G06F9/30076
摘要： A secure promotion mechanism promotes a current privilege level of a processor in a computer system. The current privilege level controls application instruction execution in the computer system by controlling accessibility to system resources. An operating system performs a privilege promotion instruction, which is stored in a first page of memory not writeable by an application instructions at a first privilege level. The privilege promotion instruction reads a stored previous privilege level state, compares the read previous privilege level state to the current privilege level, and if the previous privilege level state is equal to or less privileged than the current privilege level, promotes the current privilege level to a second privilege level which is higher than the first privilege level.
摘要翻译：安全促销机制促进计算机系统中处理器的当前特权级别。当前的权限级别通过控制系统资源的可访问性来控制计算机系统中的应用程序指令执行。操作系统执行特权提升指令，该指令被存储在不能由第一特权级别的应用指令写入的存储器的第一页中。特权提升指令读取存储的先前的权限级别状态，将读取的先前权限级别状态与当前权限级别进行比较，并且如果先前的权限级别状态等于或低于当前权限级别的权限，则将当前权限级别提升到第二个权限级别高于第一个权限级别。

5. 发明授权

US5922065A Processor utilizing a template field for encoding instruction sequences in a wide-word format 失效
标题翻译：处理器利用模板字段来编码宽字格式的指令序列
公开(公告)号：US5922065A
公开(公告)日：1999-07-13
申请号：US949279
申请日：1997-10-13
申请人： James M. Hull , Kent Fielden , Hans Mulden , Harshvardhan Sharangpani
发明人： James M. Hull , Kent Fielden , Hans Mulden , Harshvardhan Sharangpani
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30094 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/3853
摘要： A processor having a large register file utilizes a template field for ening a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of the processor are similarly categorized into different types, wherein each instruction type may be executed on one or more of the execution unit types. The instructions are grouped together into 128-bit sized and aligned containers called bundles, with each bundle includes a plurality of instruction slots and a template field that specifies the mapping of the instruction slots to the execution unit types.
摘要翻译：具有大寄存器文件的处理器利用模板字段来编码长指令字格式的一组最有用的指令序列。处理器的指令集包括作为多种不同指令类型之一的指令。处理器的执行单元类似地分类为不同类型，其中每个指令类型可以在一个或多个执行单元类型上执行。这些指令被分组在128位大小和对齐的容器中，称为捆绑包，每个包包括多个指令槽和模板字段，其指定指令槽与执行单元类型的映射。

6. 发明授权

US07155471B2 Method and system for determining the correct rounding of a function 失效
标题翻译：确定函数正确舍入的方法和系统
公开(公告)号：US07155471B2
公开(公告)日：2006-12-26
申请号：US10366003
申请日：2003-02-12
申请人： Peter Markstein , Dale Morris , James M. Hull
发明人： Peter Markstein , Dale Morris , James M. Hull
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/49957
摘要： A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and examining the portion of extra precision in the result known as the discriminant. If a critical pattern is found in the discriminant, this indicates that standard rounding may give an incorrect result and further calculation is needed. The method can work for various rounding modes and types of floating point representations. The method can be implemented in a system as part of a processor instruction set or any combination of hardware, microcode, and software.
摘要翻译：一种方法和系统用于确定浮点函数的正确舍入。该方法包括执行浮点函数的精度高于所需的精度，并检查称为判别式的结果中的额外精度部分。如果在判别式中发现关键模式，则表示标准舍入可能会给出不正确的结果，需要进一步的计算。该方法可以用于各种舍入模式和浮点表示的类型。该方法可以作为处理器指令集或硬件，微代码和软件的任何组合的一部分在系统中实现。

7. 发明授权

US06279126B1 Method for verifying that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically 失效
标题翻译：用于当端点模式被动态改变时验证处理器正在以适当的端模式执行指令的方法
公开(公告)号：US06279126B1
公开(公告)日：2001-08-21
申请号：US09183572
申请日：1998-10-30
申请人： Vishal Malik , Alejandro Quiroz , Martin J. Whittaker , James M. Hull , Michael R. Morrell
发明人： Vishal Malik , Alejandro Quiroz , Martin J. Whittaker , James M. Hull , Michael R. Morrell
IPC分类号： G06F1126
CPC分类号： G06F9/30043 , G06F7/768 , G06F9/30189 , G06F9/34 , G06F9/3802 , G06F11/263 , G06F11/28
摘要： A method verifies that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically. In accordance with the present invention, a test suite written and compiled in big endian mode is loaded into memory. The test suite is converted to little endian mode and stored back to memory. Next, the processor status is changed from big endian mode to little endian mode, and the test suite is executed. Finally, the results of the test suite are examined to ensure that the processor properly executed the instructions in little endian mode.
摘要翻译：当endian模式动态地改变时，一种方法验证处理器正在正确的端模式下执行指令。根据本发明，以大端模式编写和编译的测试套件被加载到存储器中。测试套件转换为小端模式并存储回内存。接下来，处理器状态从大端模式改变为小端模式，并且执行测试套件。最后，检查测试套件的结果，以确保处理器以小端模式正确执行指令。

8. 发明授权

US5515522A Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache 失效
标题翻译：由位于处理器外部的输入/输出适配器使用的相干索引生成，用于检测更新的数据版本是否驻留在缓存内
公开(公告)号：US5515522A
公开(公告)日：1996-05-07
申请号：US201433
申请日：1994-02-24
申请人： K. Monroe Bridges , William R. Bryg , Stephen G. Burger , James M. Hull , Michael L. Ziegler
发明人： K. Monroe Bridges , William R. Bryg , Stephen G. Burger , James M. Hull , Michael L. Ziegler
IPC分类号： G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0835
摘要： A computing system includes a memory bus, a main memory, an I/O adapter and a processor. The main memory, the I/O adapter and the processor are connected to the bus. The I/O adapter includes a translation map. The translation map maps I/O page numbers to memory address page numbers. The translation map includes coherence indices. The processor includes a cache and an instruction execution means. The instruction execution means generates coherence indices to be stored in the translation map. The instruction execution means performs in hardware a hash operation to generate the coherence indices.
摘要翻译：计算系统包括存储器总线，主存储器，I / O适配器和处理器。主存储器，I / O适配器和处理器连接到总线。 I / O适配器包括翻译图。翻译地图将I / O页码映射到内存地址页码。翻译地图包括一致性指标。处理器包括缓存和指令执行装置。指令执行装置生成要存储在转换图中的一致性索引。指令执行装置在硬件中执行散列操作以产生相干指数。

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