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1. 发明申请

US20070020856A1 Process for forming an electronic device including discontinuous storage elements 失效
标题翻译：用于形成包括不连续存储元件的电子设备的方法
公开(公告)号：US20070020856A1
公开(公告)日：2007-01-25
申请号：US11188935
申请日：2005-07-25
申请人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L21/7624 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336
摘要： forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译：在形成不连续的存储元件之后，在沟槽内形成第一栅电极。至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。

2. 发明申请

US20070018222A1 Electronic device including discontinuous storage elements 有权
标题翻译：电子设备包括不连续的存储元件
公开(公告)号：US20070018222A1
公开(公告)日：2007-01-25
申请号：US11188999
申请日：2005-07-25
申请人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译：电子设备可以包括位于沟槽内的不连续存储元件。在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。电子设备还可以包括位于沟槽内的不连续存储元件的一部分。电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。

3. 发明申请

US20070134888A1 Back-gated semiconductor device with a storage layer and methods for forming thereof 有权
标题翻译：具有存储层的后门控半导体器件及其形成方法
公开(公告)号：US20070134888A1
公开(公告)日：2007-06-14
申请号：US11300077
申请日：2005-12-14
申请人： Craig Swift , Gowrishankar Chindalore , Thuy Dao , Michael Sadd
发明人： Craig Swift , Gowrishankar Chindalore , Thuy Dao , Michael Sadd
IPC分类号： H01L21/30
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L21/84 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.
摘要翻译：制造半导体器件的方法包括提供第一晶片并提供具有第一侧和第二侧的第二晶片，所述第二晶片包括半导体衬底，存储层和栅极材料层。存储层可以位于半导体结构和栅极材料层之间，并且存储层可以比半导体结构更靠近第二晶片的第一侧。该方法还包括将第二晶片的第一侧布置到第一晶片。该方法还包括去除半导体结构的第一部分以在结合之后留下半导体结构层。该方法还包括形成具有沟道区的晶体管，其中沟道区的至少一部分由半导体结构的层形成。

4. 发明申请

US20070134867A1 Floating gate non-volatile memory and method thereof 有权
标题翻译：浮动门非易失性存储器及其方法
公开(公告)号：US20070134867A1
公开(公告)日：2007-06-14
申请号：US11302937
申请日：2005-12-14
申请人： Michael Sadd , Gowrishankar Chindalore , Cheong Hong
发明人： Michael Sadd , Gowrishankar Chindalore , Cheong Hong
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/7881
摘要： A method is provided which includes forming a first gate overlying a major surface of an electronic device substrate and forming a second gate overlying and spaced apart from the first gate. The method further includes forming a charge storage structure horizontally adjacent to, and continuous along, the first gate and the second gate, wherein a major surface of the charge storage structure is substantially vertical to the major surface of the substrate.
摘要翻译：提供了一种方法，其包括形成覆盖在电子器件基板的主表面上的第一栅极并且形成覆盖并与第一栅极间隔开的第二栅极。该方法还包括形成电荷存储结构，该电荷存储结构沿着第一栅极和第二栅极水平相邻并连续地延伸，其中电荷存储结构的主表面基本上垂直于衬底的主表面。

5. 发明申请

US20070018232A1 Nonvolatile storage array with continuous control gate employing hot carrier injection programming 有权
标题翻译：具有采用热载流子注入编程的连续控制栅极的非易失存储阵列
公开(公告)号：US20070018232A1
公开(公告)日：2007-01-25
申请号：US11188582
申请日：2005-07-25
申请人： Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/4232 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7923
摘要： An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
摘要翻译：存储单元阵列包括限定在半导体衬底中的第一沟槽下面的第一源极/漏极区域和衬底中的第二沟槽下面的第二源极/漏极区域。电荷存储堆叠线路中的每个沟槽，其中电荷存储堆叠包括不连续存储元件（DSE）层。控制门覆盖在第一沟槽上。控制栅极可以垂直于沟槽延伸并穿过第一和第二沟槽。在另一实现中，控制栅极与沟槽平行地延伸。存储单元可以包括占据第一和第二沟槽之间的衬底的上表面的一个或多个扩散区域。扩散区域可以驻留在平行于沟槽的第一和第二控制栅极之间。或者，一对扩散区域可以发生在垂直于沟槽的控制栅极的任一侧上。

6. 发明申请

US20070020831A1 Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming 有权
标题翻译：使用热载流子注入编程的连续控制栅极制造非易失性存储阵列的方法
公开(公告)号：US20070020831A1
公开(公告)日：2007-01-25
申请号：US11188583
申请日：2005-07-25
申请人： Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L21/8234
CPC分类号： H01L29/7887 , B82Y10/00 , H01L27/115 , H01L27/11519 , H01L27/11556 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/7923 , H01L29/7926
摘要： A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
摘要翻译：制造存储单元阵列的方法包括在半导体衬底中限定的第一沟槽下面的第一源极/漏极区域和在衬底中的第二沟槽下面的第二源极/漏极区域。电荷存储堆叠线路中的每个沟槽，其中电荷存储堆叠包括不连续存储元件（DSE）层。控制门覆盖在第一沟槽上。控制栅极可以垂直于沟槽延伸并穿过第一和第二沟槽。在另一实现中，控制栅极与沟槽平行地延伸。存储单元可以包括占据第一和第二沟槽之间的衬底的上表面的一个或多个扩散区域。扩散区域可以驻留在平行于沟槽的第一和第二控制栅极之间。或者，一对扩散区域可以发生在垂直于沟槽的控制栅极的任一侧上。

7. 发明申请

US20060046406A1 Programming, erasing, and reading structure for an NVM cell 有权
标题翻译： NVM单元的编程，擦除和读取结构
公开(公告)号：US20060046406A1
公开(公告)日：2006-03-02
申请号：US10930892
申请日：2004-08-31
申请人： Gowrishankar Chindalore , James Burnett , Craig Swift , Ramachandran Muralidhar
发明人： Gowrishankar Chindalore , James Burnett , Craig Swift , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L29/1608 , H01L29/267 , H01L29/66833 , H01L29/7881
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.
摘要翻译：非易失性存储器（NVM）具有硅锗（SiGe）漏极和硅碳（SiC）源。作为SiC的源提供通道上的应力，其改善N沟道迁移率。 SiC也具有比衬底更大的带隙，这是硅。这导致通过冲击电离产生电子/空穴对更困难。因此，在读取期间使用SiC区域用于漏极是有利的。 SiGe用作编程和擦除的漏极。具有比硅衬底更小的带隙的SiGe通过在较低电压电平下通过产生电子/空穴对的冲击电离和通过频带隧穿产生电子空穴/对来改善擦除来改善编程。

8. 发明申请

US20070019472A1 Electronic device including a memory array and conductive lines 有权
标题翻译：电子设备包括存储器阵列和导线
公开(公告)号：US20070019472A1
公开(公告)日：2007-01-25
申请号：US11188898
申请日：2005-07-25
申请人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
发明人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.
摘要翻译：电子电路可以包括第一存储单元和第二存储单元。在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。在另一方面，第一和第二存储器单元连接到相同的位线。当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

9. 发明申请

US20060076586A1 Virtual ground memory array and method therefor 有权
公开(公告)号：US20060076586A1
公开(公告)日：2006-04-13
申请号：US10961295
申请日：2004-10-08
申请人： Craig Swift , Gowrishankar Chindalore , Laureen Parker
发明人： Craig Swift , Gowrishankar Chindalore , Laureen Parker
IPC分类号： H01L29/772 , H01L21/8234
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/926 , Y10S438/962
摘要： A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.

10. 发明申请

US20060063328A1 Programming and erasing structure for a floating gate memory cell and method of making 有权
标题翻译：浮动存储单元的编程和擦除结构及其制作方法
公开(公告)号：US20060063328A1
公开(公告)日：2006-03-23
申请号：US10944244
申请日：2004-09-17
申请人： Gowrishankar Chindalore , Craig Swift
发明人： Gowrishankar Chindalore , Craig Swift
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.
摘要翻译：浮动栅极存储单元具有浮置栅极，其中存在两个浮置栅极层。蚀刻顶层以在顶层中提供轮廓，同时保持下层不变。控制栅极跟随浮动栅极的轮廓以增加它们之间的电容。浮置栅极的两层可以是由非常薄的蚀刻停止层分离的多晶硅。该蚀刻停止层足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透明性。电子能够容易地在两层之间移动。因此，顶层的蚀刻不延伸到下层，但是为了作为连续导电层的浮动栅极的目的，第一和第二层具有电效应。

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