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    • 4. 发明授权
    • Integrated multi-wavelength Fabry-Perot filter and method of fabrication
    • 集成多波长法布里 - 珀罗滤波器及其制作方法
    • US07378346B2
    • 2008-05-27
    • US11387468
    • 2006-03-22
    • Ngoc V. LeJeffrey H. BakerDiana J. ConveyPaige M. HolmSteven M. Smith
    • Ngoc V. LeJeffrey H. BakerDiana J. ConveyPaige M. HolmSteven M. Smith
    • H01L21/302H01L21/461
    • G01J3/26G02B5/284
    • A method is provided for forming a monolithically integrated optical filter, for example, a Fabry-Perot filter, over a substrate (10). The method comprises forming a first mirror (16) over the substrate (10). A plurality of etalon material layers (32, 34, 36, 38) are formed over the mirror (16), and a plurality of etch stop layers (42, 44, 46) are formed, one each between adjacent etalon material layers (32, 34, 36, 38). A photoresist is patterned to create an opening (54) over the top etalon material layer (38) and an etch (56) is performed down to the top etch stop layer (46). An oxygen plasma (58) may be applied to convert the etch stop layer (46) within the opening (54) to silicon dioxide (57). The photoresist patterning, etching, and applying of an oxygen plasma may be repeated as desired to obtain the desired number of levels (82, 84, 86, 88). A second mirror (72) is then formed on each of the levels (82, 84, 86, 88).
    • 提供了一种用于在衬底(10)上形成单片集成滤光器(例如法布里 - 珀罗滤光片)的方法。 该方法包括在衬底(10)上形成第一反射镜(16)。 多个标准具材料层(32,34,36,38)形成在反射镜(16)上方,并且形成多个蚀刻停止层(42,44,46),每个蚀刻停止层之间相邻的标准具材料层(32 ,34,36,38)。 图案化光致抗蚀剂以在顶部标准具材料层(38)上方形成开口(54),并且向下蚀刻停止层(46)进行蚀刻(56)。 可以施加氧等离子体(58)以将开口(54)内的蚀刻停止层(46)转化为二氧化硅(57)。 可以根据需要重复光刻胶图案化,蚀刻和施加氧等离子体以获得所需数量的水平(82,84,86,88)。 然后在每个级(82,84,86,88)上形成第二反射镜(72)。
    • 5. 发明授权
    • Vertically integrated photosensor for CMOS imagers
    • 用于CMOS成像器的垂直集成光电传感器
    • US06984816B2
    • 2006-01-10
    • US10641216
    • 2003-08-13
    • Paige M. HolmJon J. Candelaria
    • Paige M. HolmJon J. Candelaria
    • H01J40/14
    • H01L27/14601H01L27/14636H01L27/14643
    • An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated photosensing components that may be readily incorporated with existing technologies for the improvement of CMOS imaging, device package form factors, weights and/or other manufacturing, device or material performance metrics.
    • 公开了一种用于提供适合于在CMOS成像应用中使用的垂直集成光敏元件的示例性系统和方法,其特别包括:经处理的CMOS层(420); 以及在垂直集成的光学有源层(320,350)中制造的光敏元件(380),其中光学活性层(320,350)被结合到CMOS层(420)和光学活性层(320,350) 位于CMOS层(420)的金属化表面(405)附近。 公开的特征和规格可以被不同地控制,配置,适配或以其他方式任意地修改,以进一步改善或以其它方式优化光敏性能或其它材料特性。 本发明的示例性实施例代表性地提供了可以容易地与现有技术结合以用于改进CMOS成像,设备封装外形,重量和/或其它制造,器件或材料性能度量的集成光敏元件。
    • 7. 发明授权
    • Method of manufacturing a distributed drive optoelectronic integrated
circuit
    • 制造分布式驱动光电集成电路的方法
    • US5221633A
    • 1993-06-22
    • US756734
    • 1991-09-09
    • Paige M. HolmGeorge W. Rhyne
    • Paige M. HolmGeorge W. Rhyne
    • H01L21/8252H01L27/15
    • H01L21/8252H01L27/15Y10S148/072
    • A method of manufacturing a transmitter optoelectronic integrated circuit (10) which comprises a double heterostructure optical emission device (11) and drive circuitry (16). The optical emission device (11) comprises a plurality of optical emission loci (21) distributed throughout an active layer (12) of the optical emission device (11). Drive circuit (16) comprises a plurality of first portions (17) and a second portion (18) wherein the plurality of first portions (17) are above the plurality of emission loci (21). Second portion (18) is integrated in a lateral orientation with respect to the plurality of first portions (17). The chemical composition of the plurality of first portions (17) are such that they are nonabsorbing to optical emissions from the optical emission device (11).
    • 一种制造发射器光电集成电路(10)的方法,其包括双异质结构光发射装置(11)和驱动电路(16)。 光发射装置(11)包括分布在光发射装置(11)的有源层(12)的多个光发射轨道(21)。 驱动电路(16)包括多个第一部分(17)和第二部分(18),其中多个第一部分(17)在多个发射轨迹(21)之上。 第二部分(18)相对于多个第一部分(17)以横向方向被一体化。 多个第一部分(17)的化学成分使得它们不吸收来自光发射装置(11)的光发射。
    • 9. 发明授权
    • Sensor packaging method and sensor packages
    • 传感器封装方法和传感器封装
    • US08659167B1
    • 2014-02-25
    • US13597824
    • 2012-08-29
    • Philip H. BowlesPaige M. HolmStephen R. HooperRaymond M. Roop
    • Philip H. BowlesPaige M. HolmStephen R. HooperRaymond M. Roop
    • H01L29/84
    • H01L23/528B81C1/0023B81C1/00238B81C2201/019B81C2203/0792H01L2224/48091H01L2924/1461H01L2924/00014H01L2924/00
    • A method (80) entails providing (82) a structure (117), providing (100) a controller element (102, 24), and bonding (116) the controller element to an outer surface (52, 64) of the structure. The structure includes a sensor wafer (92) and a cap wafer (94). Inner surfaces (34, 36) of the wafers (92, 94) are coupled together, with sensors (30) interposed between the wafers. One wafer (94, 92) includes a substrate portion (40, 76) with bond pads (42) formed on its inner surface (34, 36). The other wafer (94, 92) conceals the substrate portion (40, 76). After bonding, methodology (80) entails forming (120) conductive elements (60) on the element (102, 24), removing (126) material sections (96, 98, 107) from the wafers to expose the bond pads, forming (130) electrical interconnects (56), applying (134) packaging material (64), and singulating (138) to produce sensor packages (20, 70).
    • 方法(80)需要提供(82)结构(117),提供(100)控制器元件(102,24),并将控制器元件(116)结合(116)到结构的外表面(52,64)。 该结构包括传感器晶片(92)和盖晶片(94)。 晶片(92,94)的内表面(34,36)被耦合在一起,传感器(30)置于晶片之间。 一个晶片(94,92)包括具有形成在其内表面(34,36)上的接合焊盘(42)的衬底部分(40,76)。 另一个晶片(94,92)隐藏基板部分(40,76)。 在结合之后,方法学(80)需要在元件(102,24)上形成(120)导电元件(60),从晶片去除(126)材料部分(96,98,107)以暴露接合焊盘,形成 130)电互连(56),施加(134)包装材料(64)和单分离(138)以产生传感器封装(20,70)。