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1. 发明授权

US5819105A System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device 失效
标题翻译：处理器接口监听第一和第二级缓存的系统与总线主控设备的存储器访问并行
公开(公告)号：US5819105A
公开(公告)日：1998-10-06
申请号：US566556
申请日：1995-12-04
申请人： Michael P. Moriarty , Michael J. Collins , John E. Larson , Gary W. Thome
发明人： Michael P. Moriarty , Michael J. Collins , John E. Larson , Gary W. Thome
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00
CPC分类号： G06F12/0831 , G06F13/1605 , G06F13/1642 , G06F13/1694
摘要： A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When a PCI device executes a memory read, the processor cache and L2 cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus.
摘要翻译：存储器控制器在处理器和PCI总线与存储器系统之间提供一系列的队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作PCI到存储器队列。当PCI设备执行存储器读取时，处理器缓存和L2高速缓存与存储器读取操作并行地窥探。在窥探操作完成之前，不提供数据。如果窥探操作指示修改的位置，则在向PCI总线提供数据之前执行写回操作。如果数据在存储器和高速缓存之间是一致的，则从存储器向PCI总线提供数据。

2. 发明授权

US5938739A Memory controller including write posting queues, bus read control logic, and a data contents counter 失效
标题翻译：存储器控制器包括写入寄存队列，总线读取控制逻辑和数据内容计数器
公开(公告)号：US5938739A
公开(公告)日：1999-08-17
申请号：US811587
申请日：1997-03-05
申请人： Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
发明人： Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00 , G06F13/14
CPC分类号： G06F12/0831 , G06F13/1605 , G06F13/1642 , G06F13/1694
摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.
摘要翻译：存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作PCI到存储器队列。当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。

3. 发明授权

US5634073A System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation 失效
标题翻译：具有与不同类型的写入操作相关联的多个发布队列的系统，用于基于读取操作的类型选择性地检查一个队列
公开(公告)号：US5634073A
公开(公告)日：1997-05-27
申请号：US324246
申请日：1994-10-14
申请人： Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
发明人： Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00
CPC分类号： G06F12/0831 , G06F13/1605 , G06F13/1642 , G06F13/1694
摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.
摘要翻译：存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作PCI到存储器队列。当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。

4. 发明授权

US5634112A Memory controller having precharge prediction based on processor and PCI bus cycles 失效
标题翻译：存储器控制器具有基于处理器和PCI总线周期的预充电预测
公开(公告)号：US5634112A
公开(公告)日：1997-05-27
申请号：US324112
申请日：1994-10-14
申请人： Gary W. Thome , Michael P. Moriarty , John E. Larson
发明人： Gary W. Thome , Michael P. Moriarty , John E. Larson
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F13/1631
摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.
摘要翻译：存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作PCI到存储器队列。当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。

5. 发明授权

US5960459A Memory controller having precharge prediction based on processor and PCI bus cycles 有权
标题翻译：存储器控制器具有基于处理器和PCI总线周期的预充电预测
公开(公告)号：US5960459A
公开(公告)日：1999-09-28
申请号：US141702
申请日：1998-08-28
申请人： Gary W. Thome , Michael P. Moriarty , John E. Larson
发明人： Gary W. Thome , Michael P. Moriarty , John E. Larson
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F13/1631
摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.
摘要翻译：存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作PCI到存储器队列。当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。

6. 发明授权

US5813038A Memory controller having precharge prediction based on processor and PC bus cycles 失效
标题翻译：存储器控制器具有基于处理器和PC总线周期的预充电预测
公开(公告)号：US5813038A
公开(公告)日：1998-09-22
申请号：US802295
申请日：1997-02-18
申请人： Gary W. Thome , Michael P. Moriarty , John E. Larson
发明人： Gary W. Thome , Michael P. Moriarty , John E. Larson
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F13/1631
摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.
摘要翻译：存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作PCI到存储器队列。当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。

7. 发明授权

US5778413A Programmable memory controller having two level look-up for memory timing parameter 失效
标题翻译：可编程存储器控制器具有用于存储器定时参数的两级查找
公开(公告)号：US5778413A
公开(公告)日：1998-07-07
申请号：US606546
申请日：1996-02-26
申请人： Jeffrey C. Stevens , John E. Larson , Gary W. Thome , Michael J. Collins , Michael Moriarty
发明人： Jeffrey C. Stevens , John E. Larson , Gary W. Thome , Michael J. Collins , Michael Moriarty
IPC分类号： G06F12/06 , G06F13/16 , G06F13/42 , G06F12/00 , G06F13/10
CPC分类号： G06F13/4243 , G06F13/1689 , G06F13/1694
摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the Peripheral Component Interconnect (PCI) to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.
摘要翻译：存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作到存储器队列的外围组件互连（PCI）。当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规动态随机存取存储器周期的特定部分的时钟周期数。

8. 发明授权

US5524235A System for arbitrating access to memory with dynamic priority assignment 失效
标题翻译：用动态优先级分配仲裁访问内存的系统
公开(公告)号：US5524235A
公开(公告)日：1996-06-04
申请号：US324011
申请日：1994-10-14
申请人： John E. Larson , Michael Moriarty , Michael J. Collins , Gary W. Thome
发明人： John E. Larson , Michael Moriarty , Michael J. Collins , Gary W. Thome
IPC分类号： G06F13/16 , G06F13/18
CPC分类号： G06F13/1605 , G06F13/18
摘要： An arbiter circuit for controlling access to the main memory for requests asserted by the microprocessor, the refresh controller and PCI bus masters. Generally, the priority of the memory requests are as follows, with some exceptions: (1) second refresh request; (2) processor-to-memory write request; (3) memory-to-processor read request; (4) PCI-to-memory write request; (5) memory-to-PCI read request; and (6) first refresh request. The second refresh request indicates that two refreshes are outstanding. When that occurs, both outstanding refresh requests are assigned the highest priority. The processor-to-memory write request is always higher in priority than other memory requests except the second refresh. However, under certain conditions, the processor-to-memory write requests is held off to allow other cycles to proceed. The memory-to-processor read request is generally higher in priority than the PCI write and read requests, unless certain conditions occur to override that priority. PCI-to-memory write requests are always higher in priority than memory-to-PCI read requests.
摘要翻译：一个仲裁器电路，用于控制对主存储器的访问，该请求由微处理器，刷新控制器和PCI总线主设备所请求。通常，存储器请求的优先级如下，但有一些例外：（1）第二刷新请求; （2）处理器到存储器写请求; （3）存储器到处理器读取请求; （4）PCI到存储器写请求; （5）内存到PCI的读取请求; 和（6）第一次刷新请求。第二次刷新请求表明两次刷新未完成。发生这种情况时，两个未完成的刷新请求都将被分配最高优先级。除了第二次刷新，处理器到存储器写请求的优先级总是高于其他内存请求。然而，在某些条件下，处理器到存储器写入请求被关闭以允许其他周期继续进行。存储器到处理器的读取请求的优先级通常高于PCI写入和读取请求，除非发生某些条件来覆盖该优先级。 PCI到内存写请求的优先级要高于内存到PCI的读请求。

9. 发明授权

US5604884A Burst SRAMS for use with a high speed clock 失效
标题翻译：突发SRAMS用于高速时钟
公开(公告)号：US5604884A
公开(公告)日：1997-02-18
申请号：US34288
申请日：1993-03-22
申请人： Gary W. Thome , Michael J. Collins
发明人： Gary W. Thome , Michael J. Collins
IPC分类号： G06F13/42 , G11C7/10 , G11C7/22 , G11C8/18 , G06F13/28
CPC分类号： G11C8/18 , G06F13/4243 , G11C7/1018 , G11C7/22
摘要： Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.
摘要翻译：突发SRAM被设计为以对应于第一时钟信号的频率但能够使用较高频率时钟信号操作的给定数据速率进行操作。突发SRAM优选地并入计算机系统中耦合到处理器总线的第二级高速缓冲存储器中，其中计算机系统优选地基于66MHz P5微处理器。优选地并入存储器控制器内的高速缓存控制器通过提供地址负载和地址提前信号来控制第二级高速缓冲存储器的操作。突发SRAM能够识别更快的时钟脉冲，以及在地址负载和地址提前信号上断言的较短脉冲。地址控制信号被断言，然后在更快的时钟信号的连续时钟周期期间被否定，使得突发SRAM有效地以对应于较低频率时钟信号的相同数据速率工作。

10. 发明授权

US5778433A Computer system including a first level write-back cache and a second level cache 失效
标题翻译：计算机系统包括第一级回写高速缓存和第二级高速缓存
公开(公告)号：US5778433A
公开(公告)日：1998-07-07
申请号：US665244
申请日：1996-06-17
申请人： Michael J. Collins , Gary W. Thome
发明人： Michael J. Collins , Gary W. Thome
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0897
摘要： An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.
摘要翻译：一种用于在解码特殊冲洗确认周期时监视和解码处理器总线周期并刷新第二级高速缓存的装置。 CPU优选地包括内部高速缓存和用于接收命令CPU冲洗其内部高速缓存的信号的刷新输入。通过执行任何必要的循环来刷新脏数据到主存储器后，CPU执行特殊的刷新确认周期，以通知外部设备冲洗过程已经完成。缓存控制器检测刷新确认周期，并向第二级缓存提供刷新信号。然后，缓存控制器向CPU提供周期信号的结束以指示冲洗周期已被确认。

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