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1. 发明授权

US09519324B2 Local power gate (LPG) interfaces for power-aware operations 有权
标题翻译：用于电源感知操作的本地电源门（LPG）接口
公开(公告)号：US09519324B2
公开(公告)日：2016-12-13
申请号：US14225612
申请日：2014-03-26
申请人： Michael Mishaeli , Ron Gabor , Robert C. Valentine , Alex Gerber , Zeev Sperber
发明人： Michael Mishaeli , Ron Gabor , Robert C. Valentine , Alex Gerber , Zeev Sperber
IPC分类号： G06F1/32 , G06F9/22
CPC分类号： G06F1/3206 , G06F1/3287 , G06F9/22 , Y02D10/171
摘要： Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.
摘要翻译：描述了用于功率感知操作的本地电源门（LPG）接口的技术。处理器包括核心的本地门控电路，核心的主核心电路，主核心和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为本地门控电路供电。主核心解码一组指令的第一指令以执行指定长度的第一功率感知操作，包括计算用于执行的执行代码路径。主核心监控LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择其中一条代码路径，并向LPG硬件发出提示，以启动本地并且继续执行第一功率感知操作，而不等待本地门控电路被加电。

2. 发明授权

US08909988B2 Recoverable parity and residue error 有权
标题翻译：可恢复奇偶校验和残差误差
公开(公告)号：US08909988B2
公开(公告)日：2014-12-09
申请号：US13436319
申请日：2012-03-30
申请人： Zeev Sperber , Ofer Levy , Michael Mishaeli , Ron Gabor
发明人： Zeev Sperber , Ofer Levy , Michael Mishaeli , Ron Gabor
IPC分类号： G06F11/00
CPC分类号： G06F11/1405 , G06F11/1032
摘要： An error recovery unit that may include error logic to detect an error in a dispatch port and timestamp logic configured to generate a timestamp for the error. The error recovery unit may also include check logic to determine if an instruction associated with the error has been retired based on the timestamp. If the instruction has been retired, a machine check error logic may be initiated. If the instruction has not been retired, an error correction logic may be initiated to recover the error and to re-execute the instruction. Thus, speculative errors may be recovered without the need for calling the machine check error, which is undesirable because of its catastrophic nature. Therefore, machine check errors may be significantly reduced.
摘要翻译：错误恢复单元，其可以包括用于检测调度端口中的错误的错误逻辑和被配置为生成错误的时间戳的时间戳逻辑。错误恢复单元还可以包括检查逻辑，以基于时间戳来确定与错误相关联的指令是否已经退休。如果指令已经停止，则可能启动机器检查错误逻辑。如果指令还没有退出，则可以启动纠错逻辑来恢复错误并重新执行指令。因此，可以恢复投机错误，而不需要调用机器检查错误，这是因为其灾难性质而不期望的。因此，机器检查错误可能会显着降低。

3. 发明申请

US20140006817A1 Performing Local Power Gating In A Processor 有权
标题翻译：在处理器中执行本地电源门控
公开(公告)号：US20140006817A1
公开(公告)日：2014-01-02
申请号：US13534601
申请日：2012-06-27
申请人： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
发明人： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3869 , G06F9/3885 , Y02B70/123 , Y02B70/126 , Y02D10/152 , Y02D10/171
摘要： In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括执行单元，用于执行第一类型的指令，耦合到执行单元的本地电源门电路，以在第二执行单元执行第二类型的指令时对所述执行单元进行电源门控，以及控制器，其耦合到所述本地电源门电路，以使得当指令流不包括所述第一类型的指令时，所述控制器对所述执行单元进行供电。描述和要求保护其他实施例。

4. 发明申请

US20140223226A1 APPARATUS AND METHOD FOR DETECTING AND RECOVERING FROM DATA FETCH ERRORS 审中-公开
标题翻译：用于从数据触发错误中检测和恢复的装置和方法
公开(公告)号：US20140223226A1
公开(公告)日：2014-08-07
申请号：US13994609
申请日：2011-12-22
申请人： Theodros Yigzaw , Geeyarpuram N. Santhanakrushnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrushnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
IPC分类号： G06F11/14
CPC分类号： G06F11/1405 , G06F11/1064
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
摘要翻译：描述了用于检测和校正处理器核心内的数据获取错误的装置和方法。例如，用于检测和从数据获取错误中恢复的指令处理装置的一个实施例包括：具有多个指令处理阶段的至少一个处理器核心，包括数据获取阶段和退休阶段; 以及与处理级通信的错误处理逻辑，以执行以下操作：响应于由数据获取级执行的数据获取操作，检测与数据相关联的错误; 并且响应地执行一个或多个操作以确保该错误不会在退休阶段内破坏处理器核心的体系结构状态。

5. 发明授权

US09229524B2 Performing local power gating in a processor 有权
标题翻译：在处理器中执行本地电源门控
公开(公告)号：US09229524B2
公开(公告)日：2016-01-05
申请号：US13534601
申请日：2012-06-27
申请人： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
发明人： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
IPC分类号： G06F1/32 , G06F9/30 , G06F9/38
CPC分类号： G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3869 , G06F9/3885 , Y02B70/123 , Y02B70/126 , Y02D10/152 , Y02D10/171
摘要： In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括执行单元，用于执行第一类型的指令，耦合到执行单元的本地电源门电路，以在第二执行单元执行第二类型的指令时对所述执行单元进行电源门控，以及控制器，其耦合到所述本地电源门电路，以使得当指令流不包括所述第一类型的指令时，所述控制器对所述执行单元进行供电。描述和要求保护其他实施例。

6. 发明授权

US10223204B2 Apparatus and method for detecting and recovering from data fetch errors 有权
公开(公告)号：US10223204B2
公开(公告)日：2019-03-05
申请号：US13994609
申请日：2011-12-22
申请人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
IPC分类号： G06F11/00 , G06F11/14 , G06F11/10
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

7. 发明申请

US20150261590A1 CONDITIONAL MEMORY FAULT ASSIST SUPPRESSION 有权
标题翻译：条件记忆障碍协助抑制
公开(公告)号：US20150261590A1
公开(公告)日：2015-09-17
申请号：US14214910
申请日：2014-03-15
申请人： Zeev Sperber , Robert Valentine , Offer Levy , Michael Mishaeli , Gal Ofir
发明人： Zeev Sperber , Robert Valentine , Offer Levy , Michael Mishaeli , Gal Ofir
IPC分类号： G06F11/07
CPC分类号： G06F11/079 , G06F11/0721 , G06F11/073
摘要： In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode stage to decode one or more instruction specifying: a set of memory operations, one or more register, and one or more memory address. One or more execution units, responsive to the one or more decoded instruction, generate said one or more memory address for the set of memory operations. Instruction execution logic records one or more fault suppress bits to indicate whether one or more portion of the set of memory operations are masked. Fault generation logic is suppressed from considering a memory fault corresponding to a faulting one of the set of memory operations when said faulting one of the set of memory operations corresponds to a portion of the set of memory operations that is indicated as masked by said one or more fault suppress bits.
摘要翻译：在一些公开的实施例中，指令执行逻辑提供条件存储器故障辅助抑制。处理器的一些实施例包括解码级，以对一个或多个指令进行解码，该指令指定：一组存储器操作，一个或多个寄存器和一个或多个存储器地址。响应于一个或多个解码指令的一个或多个执行单元为该组存储器操作生成所述一个或多个存储器地址。指令执行逻辑记录一个或多个故障抑制位以指示该组存储器操作中的一个或多个部分被屏蔽。当所述一组存储器操作中的所述故障之一对应于由所述一组存储器操作屏蔽的所述一组存储器操作的一部分时，故障产生逻辑被抑制为考虑与所述一组存储器操作中的故障的一个存储器操作相对应的存储器故障，更多的故障抑制位。

8. 发明申请

US20160179545A1 INSTRUCTION AND LOGIC FOR REGISTER BASED HARDWARE MEMORY RENAMING 审中-公开
标题翻译：基于注册的硬件存储器恢复的指令和逻辑
公开(公告)号：US20160179545A1
公开(公告)日：2016-06-23
申请号：US14581268
申请日：2014-12-23
申请人： Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
发明人： Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/30043 , G06F9/30101 , G06F9/30116 , G06F9/3802 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/3891
摘要： A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.
摘要翻译：处理器包括核心，存储器子系统，预测器模块和存储器重命名模块。预测器模块可以包括用于识别存储指令和加载指令之间的依赖性的第一逻辑，以及基于所识别的依赖关系将存储器重命名（MRN）寄存器分配给存储指令和加载指令的第二逻辑。此外，存储器重命名模块可以包括第三逻辑，用于基于所分配的MRN寄存器将与存储指令相关联的第一逻辑寄存器中的信息直接复制到与加载指令相关联的第二逻辑寄存器。

9. 发明授权

US09904547B2 Packed data rearrangement control indexes generation processors, methods, systems and instructions 有权
公开(公告)号：US09904547B2
公开(公告)日：2018-02-27
申请号：US13977217
申请日：2011-12-22
申请人： Elmoustapha Ould-Ahmed-Vall , Seth Abraham , Robert Valentine , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Seth Abraham , Robert Valentine , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving a packed data rearrangement control indexes generation instruction. The packed data rearrangement control indexes generation instruction indicates a destination storage location. A result is stored in the destination storage location in response to the packed data rearrangement control indexes generation instruction. The result includes a sequence of at least four non-negative integers representing packed data rearrangement control indexes. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.

10. 发明授权

US09542154B2 Fused multiply add operations using bit masks 有权
标题翻译：融合乘法使用位掩码添加操作
公开(公告)号：US09542154B2
公开(公告)日：2017-01-10
申请号：US13926175
申请日：2013-06-25
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F7/483 , G06F7/544 , G06F7/76
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/764
摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
摘要翻译：提供了执行融合乘法（FMA）操作的系统和方法。在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。可以使用掩码来使用加法器来执行FMA操作的相加部分。如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

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