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1. 发明授权

US09519324B2 Local power gate (LPG) interfaces for power-aware operations 有权
标题翻译：用于电源感知操作的本地电源门（LPG）接口
公开(公告)号：US09519324B2
公开(公告)日：2016-12-13
申请号：US14225612
申请日：2014-03-26
申请人： Michael Mishaeli , Ron Gabor , Robert C. Valentine , Alex Gerber , Zeev Sperber
发明人： Michael Mishaeli , Ron Gabor , Robert C. Valentine , Alex Gerber , Zeev Sperber
IPC分类号： G06F1/32 , G06F9/22
CPC分类号： G06F1/3206 , G06F1/3287 , G06F9/22 , Y02D10/171
摘要： Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.
摘要翻译：描述了用于功率感知操作的本地电源门（LPG）接口的技术。处理器包括核心的本地门控电路，核心的主核心电路，主核心和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为本地门控电路供电。主核心解码一组指令的第一指令以执行指定长度的第一功率感知操作，包括计算用于执行的执行代码路径。主核心监控LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择其中一条代码路径，并向LPG硬件发出提示，以启动本地并且继续执行第一功率感知操作，而不等待本地门控电路被加电。

2. 发明申请

US20160179545A1 INSTRUCTION AND LOGIC FOR REGISTER BASED HARDWARE MEMORY RENAMING 审中-公开
标题翻译：基于注册的硬件存储器恢复的指令和逻辑
公开(公告)号：US20160179545A1
公开(公告)日：2016-06-23
申请号：US14581268
申请日：2014-12-23
申请人： Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
发明人： Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/30043 , G06F9/30101 , G06F9/30116 , G06F9/3802 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/3891
摘要： A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.
摘要翻译：处理器包括核心，存储器子系统，预测器模块和存储器重命名模块。预测器模块可以包括用于识别存储指令和加载指令之间的依赖性的第一逻辑，以及基于所识别的依赖关系将存储器重命名（MRN）寄存器分配给存储指令和加载指令的第二逻辑。此外，存储器重命名模块可以包括第三逻辑，用于基于所分配的MRN寄存器将与存储指令相关联的第一逻辑寄存器中的信息直接复制到与加载指令相关联的第二逻辑寄存器。

3. 发明申请

US20180095759A1 SUSPENDABLE LOAD ADDRESS TRACKING INSIDE TRANSACTIONS 审中-公开
公开(公告)号：US20180095759A1
公开(公告)日：2018-04-05
申请号：US15282011
申请日：2016-09-30
申请人： Raanan Sade , Roman Dementiev , Ravi Rajwar , Ady Tal , Alex Gerber
发明人： Raanan Sade , Roman Dementiev , Ravi Rajwar , Ady Tal , Alex Gerber
IPC分类号： G06F9/30 , G06F12/0855 , G06F12/123 , G06F12/0875
CPC分类号： G06F9/30043 , G06F9/3838 , G06F9/466 , G06F9/467 , G06F12/0857 , G06F12/0862 , G06F12/0875 , G06F12/1027 , G06F12/12 , G06F12/123 , G06F2212/1024 , G06F2212/452 , G06F2212/6022
摘要： Suspendable load address tracking inside transactions is disclosed. An example processing device of implementations of the disclosure includes a transactional memory (TM) read set tracking component circuitry to identify a suspend read tracking instruction within a transaction executed by the processing device, mark load instructions occurring in the transaction subsequent to the identified suspend read tracking instruction with a suspend attribute, wherein the addresses corresponding to the marked load instructions are excluded from a read set maintained for the transaction, identify a resume read tracking instruction within the transaction, and stop marking the load instructions occurring subsequent to the identified resume read tracking instruction with the suspend attribute.

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