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    • 1. 发明授权
    • Semaphore enhancement to allow bank selection of a shared resource
memory device
    • 信号量增强,允许银行选择共享资源存储设备
    • US6108756A
    • 2000-08-22
    • US785662
    • 1997-01-17
    • Michael MillerJohn MickJeff SmithMark Baumann
    • Michael MillerJohn MickJeff SmithMark Baumann
    • G06F9/46G06F12/02
    • G06F9/52
    • A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.
    • 具有用于与左(205)和右(206)电子设备进行通信的左(203)和右(204)端口的存储设备(201)包括存储体(401-0差分401-7),信号量逻辑(302) ,以及端口耦合电路(403,404,405-0,差异405-7,406-0,差异406-7,407-0,差异407-7)。 信号量逻辑响应于来自左和右电子设备的存储体访问请求而在第一接收的基础上产生存储体存取授权信号(313,314),并且端口耦合电路响应于所选择的存储体耦合到左端口和右端口 银行存取授权信号。 存储设备中还包括邮箱寄存器(2500-0L DIFFERENCE 2500-3L,2500-0R差分2500-3R),中断产生电路(2514-0L差分2514-3L,2514-0R差分2514-3R,2900 ,3000,307,308)以及中断状态和原因寄存器(3101L差分3102L,3101R差分3102R,3301L差分3302L,3301R差分3302R)。 左右电子设备使用邮箱寄存器相互发送消息,无需等待。 中断产生电路产生中断以在其银行访问请求被授予时通知左和右电子设备,并且当消息已被写入其中一个邮箱寄存器时。 中断状态和原因寄存器提供关于左和右电子设备被授权访问哪些存储器的信息,哪些邮箱寄存器包含用于它们的消息。
    • 2. 发明授权
    • Multi-ported memory architecture using single-ported RAM
    • 使用单端口RAM的多端口存储器架构
    • US06212607B1
    • 2001-04-03
    • US08783923
    • 1997-01-17
    • Michael MillerJohn MickJeff SmithMark BaumannChris Schott
    • Michael MillerJohn MickJeff SmithMark BaumannChris Schott
    • G06F1200
    • G11C7/1075G11C2207/104
    • A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0˜401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0˜405-7, 406-0˜406-7, 407-0˜407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L˜2500-3L, 2500-0R˜2500-3R), interrupt generating circuitry (2514-0L˜2514-3L, 2514-0R˜2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L˜3102L, 3101R˜3102R, 3301L˜3302L, 3301R˜3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.
    • 具有用于与左(205)和右(206)电子设备通信的左(203)和右(204)端口的存储设备(201)包括存储体(401-0〜401-7),信号量逻辑(302) ,和端口耦合电路(403,404,405-0〜405-7,406-0〜406-7,407-0〜407-7)。 信号量逻辑响应于来自左和右电子设备的存储体访问请求而在第一接收的基础上产生存储体存取授权信号(313,314),并且端口耦合电路响应于所选择的存储体耦合到左端口和右端口 银行存取授权信号。 内存中还包括邮箱寄存器(2500-0L〜2500-3L,2500-0R〜2500-3R),中断发生电路(2514-0L〜2514-3L,2514-0R〜2514-3R,2900 ,3000,307,308),以及中断状态和原因寄存器(3101L〜3102L,3101R〜3102R,3301L〜3302L,3301R〜3302R)。 左右电子设备使用邮箱寄存器相互发送消息,无需等待。 中断产生电路产生中断以在其银行访问请求被授予时通知左和右电子设备,并且当消息已被写入其中一个邮箱寄存器时。 中断状态和原因寄存器提供关于左和右电子设备被授权访问哪些存储器的信息,哪些邮箱寄存器包含用于它们的消息。
    • 3. 发明授权
    • Mail-box design for non-blocking communication across ports of a
multi-port device
    • 用于多端口设备端口之间的非阻塞通信的邮箱设计
    • US5751638A
    • 1998-05-12
    • US786401
    • 1997-01-17
    • John MickMichael MillerJeff SmithMark Baumann
    • John MickMichael MillerJeff SmithMark Baumann
    • G06F5/10G06F9/46G11C8/16G11C13/00
    • G06F5/10G06F9/52G11C8/16
    • A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.
    • 具有用于与左(205)和右(206)电子设备进行通信的左(203)和右(204)端口的存储设备(201)包括存储体(401-0差分401-7),信号量逻辑(302) ,以及端口耦合电路(403,404,405-0,差异405-7,406-0,差异406-7,407-0,差异407-7)。 信号量逻辑响应于来自左和右电子设备的存储体访问请求而在第一接收的基础上产生存储体存取授权信号(313,314),并且端口耦合电路响应于所选择的存储体耦合到左端口和右端口 银行存取授权信号。 存储设备中还包括邮箱寄存器(2500-0L DIFFERENCE 2500-3L,2500-0R差分2500-3R),中断产生电路(2514-0L差分2514-3L,2514-0R差分2514-3R,2900 ,3000,307,308)以及中断状态和原因寄存器(3101L差分3102L,3101R差分3102R,3301L差分3302L,3301R差分3302R)。 左右电子设备使用邮箱寄存器相互发送消息,无需等待。 中断产生电路产生中断以在其银行访问请求被授予时通知左和右电子设备,并且当消息已被写入其中一个邮箱寄存器时。 中断状态和原因寄存器提供关于左和右电子设备被授权访问哪些存储器的信息,哪些邮箱寄存器包含用于它们的消息。
    • 6. 发明申请
    • AUTOMATICALLY CAPTURING IMAGES THAT INCLUDE LIGHTNING
    • 自动拍摄包含闪电的图像
    • US20130286249A1
    • 2013-10-31
    • US13456831
    • 2012-04-26
    • Jason YostShane D. VossJohn Mick
    • Jason YostShane D. VossJohn Mick
    • H04N5/225
    • H04N5/232H04N5/772
    • A method is disclosed for capturing one or more images that include a lightning strike using an image capturing device. The method is performed by one or more processors of the image capturing device. The one or more processors automatically capture a plurality of images during a period of time using the lens of the device. Each of the plurality of images is processed to detect a presence of lightning within each image. Each image is processed based, at least part, on two consecutive captured images. Images that have been determined to include the presence of lightning are stored in a memory resource of the image capturing device.
    • 公开了一种用于捕获包括使用图像捕获装置的雷击的一个或多个图像的方法。 该方法由图像捕获装置的一个或多个处理器执行。 一个或多个处理器在使用该设备的镜头的一段时间期间自动地捕获多个图像。 处理多个图像中的每一个以检测每个图像内的闪电的存在。 每个图像至少部分地基于两个连续的拍摄图像进行处理。 被确定为包括闪电存在的图像被存储在图像捕获装置的存储器资源中。