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1. 发明申请

US20070174592A1 Early conditional selection of an operand 有权
标题翻译：早期有条件地选择操作数
公开(公告)号：US20070174592A1
公开(公告)日：2007-07-26
申请号：US11336357
申请日：2006-01-20
申请人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
发明人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
IPC分类号： G06F15/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/30072 , G06F9/30036 , G06F9/30094 , G06F9/3016 , G06F9/30167
摘要： Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.
摘要翻译：由于等待操作数不被选择操作数指令使用的延迟，基于早期识别，为了完成选择操作数指令的处理而不需要这种操作数数据，可以减轻延迟。在执行之前的适当点，确定关于由选择操作数指令指定的选择标准或标准，影响选择标准的条件以及操作数的可用性。保持电路使用该确定来控制控制处理器流水线停顿的保持信号的激活和释放。如果所选择的操作数可用，即使不使用另一个操作数不可用，则跳过等待操作数数据所需的档位或提前终止档位。维持由于等待操作数而导致的停顿，直到满足选择标准并且所选择的操作数被获取并可用。

2. 发明申请

US20070038826A1 Method and system for providing an energy efficient register file 有权
标题翻译：提供能量效率寄存器文件的方法和系统
公开(公告)号：US20070038826A1
公开(公告)日：2007-02-15
申请号：US11201542
申请日：2005-08-10
申请人： James Dieffenderfer , Thomas Sartorius , Jeffrey Bridges , Michael McIlvaine , Gregory Burda
发明人： James Dieffenderfer , Thomas Sartorius , Jeffrey Bridges , Michael McIlvaine , Gregory Burda
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F9/30105 , G06F9/30141
摘要： A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.
摘要翻译：公开了一种寄存器文件。寄存器文件包括多个寄存器和解码器。解码器可以被配置为接收任何一个寄存器的地址，并且如果寻址的寄存器中的数据无效，则禁止对寻址的寄存器的读取操作。

3. 发明申请

US20060174090A1 Power efficient instruction prefetch mechanism 有权
公开(公告)号：US20060174090A1
公开(公告)日：2006-08-03
申请号：US11050932
申请日：2005-02-03
申请人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
发明人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

4. 发明申请

US20060236078A1 System and method wherein conditional instructions unconditionally provide output 有权
公开(公告)号：US20060236078A1
公开(公告)日：2006-10-19
申请号：US11106803
申请日：2005-04-14
申请人： Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges , Kenneth Dockser , Michael McIlvaine , Rodney Smith
发明人： Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges , Kenneth Dockser , Michael McIlvaine , Rodney Smith
IPC分类号： G06F9/44
CPC分类号： G06F9/30072 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

5. 发明申请

US20060206688A1 Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state 有权
标题翻译：省电方法和装置，用于基于已知的处理器状态选择性地启用CAM重命名寄存器文件中的比较器
公开(公告)号：US20060206688A1
公开(公告)日：2006-09-14
申请号：US11072849
申请日：2005-03-03
申请人： Jeffrey Bridges , James Dieffenderfer , Michael McIlvaine , Thomas Sartorius
发明人： Jeffrey Bridges , James Dieffenderfer , Michael McIlvaine , Thomas Sartorius
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/30058 , G06F1/3203 , G06F1/3275 , G06F9/384 , Y02D10/13 , Y02D10/14
摘要： A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater number of physical registers than addressable by direct use of the IRN. The renaming register file uses a content addressable memory (CAM) to provide the mapping function. The renaming register file CAM further uses current processor state information to selectively enable tag comparators to minimize power in accessing registers. When a tag comparator is not enabled it remains in a low power state. A processor using a renaming register file with low power features is also described.
摘要翻译：描述了一种用于节省电力的重命名寄存器文件。映射单元将指令寄存器号（IRN）变换为逻辑寄存器号（LRN）。重命名寄存器文件将LRN映射到物理寄存器编号（PRN），通过直接使用IRN，存在比可寻址的更大数量的物理寄存器。重命名寄存器文件使用内容可寻址存储器（CAM）来提供映射功能。重命名寄存器文件CAM还使用当前处理器状态信息来选择性地使标签比较器最小化访问寄存器的功率。当标签比较器未使能时，它保持在低功率状态。还描述了使用具有低功率特征的重命名寄存器文件的处理器。

6. 发明申请

US20060200654A1 Stop waiting for source operand when conditional instruction will not execute 审中-公开
标题翻译：当条件指令不执行时，停止等待源操作数
公开(公告)号：US20060200654A1
公开(公告)日：2006-09-07
申请号：US11073165
申请日：2005-03-04
申请人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
发明人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
IPC分类号： G06F9/44
CPC分类号： G06F9/3824 , G06F9/3001 , G06F9/30072
摘要： The delay of non-executing conditional instructions, that would otherwise be imposed while waiting for late operand data, is alleviated based on an early recognition that such instructions will not execute on the current pass through a pipeline processor. At an appropriate point prior to execution, a determination regarding the condition is made. If the condition is such that the instruction will not execute on this pass through the pipeline, the hold with regard to the conditional instruction may be terminated, that is to say skipped or stopped prior to completion of receiving all the associated operand data. Flow of the non-executing instruction through the pipeline, for example, need not wait for an earlier instruction to compute and write source operand data for use by the conditional instruction.
摘要翻译：基于早期识别这种指令将不会在当前通过流水线处理器的过程中执行的情况下，缓解不执行条件指令的延迟，否则将等待后期操作数数据施加。在执行之前的适当时刻，作出关于条件的确定。如果条件使得指令不会在通过流水线的该通过上执行，关于条件指令的保持可以被终止，也就是说在完成接收所有相关联的操作数数据之前被跳过或停止。例如，通过流水线的不执行指令的流程不需要等待较早的指令来计算和写入源操作数数据以供条件指令使用。

7. 发明申请

US20060190707A1 System and method of correcting a branch misprediction 有权
标题翻译：校正分支错误预测的系统和方法
公开(公告)号：US20060190707A1
公开(公告)日：2006-08-24
申请号：US11061981
申请日：2005-02-18
申请人： Michael McIlvaine , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Michael McIlvaine , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861
摘要： When a branch misprediction in a pipelined processor is discovered, if the mispredicted branch instruction is not the last uncommitted instruction in the pipelines, older uncommitted instructions are checked for dependency on a long latency operation. If one is discovered, all uncommitted instructions are flushed from the pipelines without waiting for the dependency to be resolved. The branch prediction is corrected, and the branch instruction and all flushed instructions older than the branch instruction are re- fetched and executed.
摘要翻译：当发现流水线处理器中的分支错误预测时，如果错误的分支指令不是管道中的最后一条未提交的指令，则会检查较长的未提交的指令对长时间延迟操作的依赖性。如果被发现，所有未提交的指令都将从管道中刷新，而不必等待解决依赖关系。校正分支预测，并重新执行分支指令和比分支指令更早的所有刷新指令。

8. 发明申请

US20060179288A1 Conditional instruction execution via emissary instruction for condition evaluation 有权
标题翻译：有条件的指令通过使用指令执行条件评估
公开(公告)号：US20060179288A1
公开(公告)日：2006-08-10
申请号：US11055919
申请日：2005-02-10
申请人： Michael McIlvaine , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith
发明人： Michael McIlvaine , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith
IPC分类号： G06F9/44
CPC分类号： G06F9/3867 , G06F9/30072 , G06F9/3017 , G06F9/30181 , G06F9/3824 , G06F9/3826
摘要： Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.
摘要翻译：通过转换条件指令来简化危险检测，条件指令可操作以在满足条件的情况下执行操作到可操作以评估条件的执行指令和用于执行操作的无条件基准指令。在基本指令停止的情况下执行执行指令。使者指令评估条件并将条件评估报告回基本指令。基于条件评估，基本指令要么被启动到管道中才能执行，要么被丢弃（或者一个NOP或者空的指令代替它）。在任一情况下，可以解决以下指令的依赖性。

9. 发明申请

US20060200686A1 Power saving methods and apparatus to selectively enable cache bits based on known processor state 有权
标题翻译：省电方法和装置，用于基于已知的处理器状态选择性地启用高速缓存位
公开(公告)号：US20060200686A1
公开(公告)日：2006-09-07
申请号：US11073284
申请日：2005-03-04
申请人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
发明人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
IPC分类号： G06F1/26
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译：描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。处理器以多种模式运行。其中一种模式限制了可以获取并执行到较长长度指令的指令。指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。处理器操作模式状态信息指示处理器的程序指定的操作模式。处理器从指令缓存器中获取指令以执行。作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取取。

10. 发明申请

US20070174584A1 Translation lookaside buffer manipulation 有权
标题翻译：翻译后备缓冲操作
公开(公告)号：US20070174584A1
公开(公告)日：2007-07-26
申请号：US11336264
申请日：2006-01-20
申请人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F9/3861 , G06F12/1027
摘要： A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.
摘要翻译：具有多级流水线的处理器包括TLB和TLB控制器。响应于TLB未命中信号，TLB控制器启动TLB重新加载，从存储器或更高级TLB请求地址转换信息，并将该信息放入TLB。处理器刷新具有缺失的虚拟地址的指令，并且重新指示该指令，从而导致在TLB接入点上方的管线的初始阶段重新插入该指令。 TLB重新启动的启动以及指令的刷新/刷新基本上并行执行，并且不会立即停止管道。重写指令在TLB接入点上方的管道中保持一段时间，直到TLB重新加载完成，这样，重写指令在下一次访问时就会在TLB中产生一个“命中”。

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