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1. 发明授权

US07463215B2 Display source divider 有权
标题翻译：显示源分频器
公开(公告)号：US07463215B2
公开(公告)日：2008-12-09
申请号：US11172125
申请日：2005-06-30
申请人： Michael Love , John Tardif , Jack Scheuer , Louis F. Coffin, III
发明人： Michael Love , John Tardif , Jack Scheuer , Louis F. Coffin, III
IPC分类号： G09G5/00
CPC分类号： G06F3/1423 , A63F2300/203 , A63F2300/30 , A63F2300/301 , A63F2300/66 , A63F2300/8082 , A63F2300/8088 , G06F3/1454
摘要： In an implementation of a display source divider, a video generation system generates a video display source that includes display data for multiple display regions which include left eye display regions and right eye display regions of head display devices. For example, a gaming system generates a video display source that includes display data for left eye display regions and right eye display regions of head display devices that each correspond to a different player of the gaming system. A display source divider receives the video display source and generates a left eye display video stream and an associated right eye display video stream for each of the head display devices.
摘要翻译：在显示源分配器的实现中，视频生成系统生成视频显示源，该视频显示源包括包括头显示装置的左眼显示区域和右眼显示区域的多个显示区域的显示数据。例如，游戏系统生成视频显示源，该视频显示源包括针对游戏系统的不同播放器的头部显示设备的左眼显示区域和右眼显示区域的显示数据。显示源分配器接收视频显示源，并为每个头显示装置生成左眼显示视频流和相关联的右眼显示视频流。

2. 发明授权

US07151576B2 Method and apparatus for modulating video signals 有权
标题翻译：用于调制视频信号的方法和装置
公开(公告)号：US07151576B2
公开(公告)日：2006-12-19
申请号：US11140848
申请日：2005-05-31
申请人： Louis F. Coffin, III
发明人： Louis F. Coffin, III
IPC分类号： H04N5/40 , H04N5/455 , H04N9/77
CPC分类号： H04N11/004
摘要： A luminance component of a video signal is modulated in a first frequency band. A first chrominance component of the video signal is modulated in a second frequency band and is mixed with an audio component. A second chrominance component of the video signal is modulated in a third frequency band. The modulated luminance component, the first modulated chrominance component, and the second modulated chrominance component are then transmitted across a communication link.
摘要翻译：在第一频带中调制视频信号的亮度分量。视频信号的第一色度分量被调制在第二频带中并与音频分量混合。在第三频带中调制视频信号的第二色度分量。调制亮度分量，第一调制色度分量和第二调制色度分量然后通过通信链路传输。

3. 发明授权

US5987579A Method and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer system 失效
标题翻译：用于在多处理器高速缓存一致计算机系统中快速启动存储器访问的方法和装置
公开(公告)号：US5987579A
公开(公告)日：1999-11-16
申请号：US825404
申请日：1997-03-27
申请人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Raymond Ng , Louis F. Coffin, III
发明人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Raymond Ng , Louis F. Coffin, III
IPC分类号： G06F13/16 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0884
摘要： In a computer system including a packet-switched bus, a method for requesting transactions such that memory accesses are initiated quickly. A master transmits a first portion of a transaction request packet having multiple portion. A memory controller receives the first portion of the transaction request, which includes a row address portion of a memory address. The memory controller initiates a memory access by applying a row address strobe signal to the row of the memory location in response to receiving the first portion of the request packet, and the master transmits any remaining portion of the transaction request. After the full memory address has been received, it is determined whether data stored at the memory location is to be read from a source other than the memory location. The memory controller aborts the memory access by inhibiting assertion of a column access strobe signal to the memory location if the data is to be read from a source other than the memory location.
摘要翻译：在包括分组交换总线的计算机系统中，用于请求事务的方法使得快速启动存储器访问。主设备发送具有多个部分的事务请求分组的第一部分。存储器控制器接收事务请求的第一部分，其包括存储器地址的行地址部分。响应于接收到请求分组的第一部分，存储器控制器通过将行地址选通信号施加到存储器位置的行来启动存储器访问，并且主机传输事务请求的任何剩余部分。在接收到完整存储器地址之后，确定存储在存储器位置的数据是否要从存储器位置以外的源读取。如果要从除存储器位置之外的源读取数据，则存储器控制器通过禁止对存储器位置的列存取选通信号的断言来中止存储器访问。

4. 发明授权

US5905998A Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system 失效
标题翻译：用于控制分组交换高速缓存一致多处理器系统中的存储器事务处理的事务激活处理器
公开(公告)号：US5905998A
公开(公告)日：1999-05-18
申请号：US858792
申请日：1997-05-19
申请人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
发明人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.
摘要翻译：多处理器计算机系统具有多个子系统和耦合到系统控制器的主存储器。一些子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器以及相应的主缓存标签集（Etag），包括由高速缓冲存储器存储的每个数据块的一个Etag。每个数据处理器包括一个接口，用于向系统控制器发送存储器事务请求，并接收来自系统控制器的高速缓存事务请求，对应于其他数据处理器的存储器事务请求。系统控制器包括事务激活逻辑，用于当其满足预定义的激活准则时激活每个所述存储器事务请求，并且用于阻止每个所述存储器事务请求直到满足预定义的激活标准。活动事务状态表存储表示已激活的存储器事务请求的状态数据，包括每个激活的事务的地址值。事务激活逻辑包括比较器逻辑，用于将每个存储器事务请求与所有激活的存储器事务请求的活动事务状态数据进行比较，以便检测特定存储器事务请求的激活是否违反预定义的激活标准。对于回写事务有一些例外，用于访问映射到相同高速缓存行的未决事务，先前激活的事务的数据块的传入事务将被阻止，直到映射到同一高速缓存行的挂起事务完成。

5. 发明授权

US5862356A Pipelined distributed bus arbitration system 失效
标题翻译：流水线分布式总线仲裁系统
公开(公告)号：US5862356A
公开(公告)日：1999-01-19
申请号：US870438
申请日：1997-06-04
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
IPC分类号： G06F15/16 , G06F13/368 , G06F13/374 , G06F15/177 , G06F13/00
CPC分类号： G06F13/368 , G06F13/374
摘要： The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e., the bus master driving the system bus, preferentially. Each arbitration task is completed within a system clock cycle regardless of processor speed. As a result, the arbitration latency for retaining the current bus master is one system clock cycle while the latency for selecting and switching bus masters is two system clock cycles. In this implementation, a last port driver is the only sub-system permitted to assert a bus request in a clock cycle and immediately drive the system bus in the next immediate clock cycle. Conversely, when a second sub-system which is not the last port driver needs to drive an inactive system bus, the second sub-system asserts its bus request line in a first clock cycle, and arbitration occurs within all the respective bus arbiters occurs in a second clock cycle.
摘要翻译：本发明提供了一种可扩展的，模块化和流水线分布式总线仲裁系统，用于有效地分辨耦合到公共系统总线的子系统（例如处理器）之间的总线争用。仲裁系统包括多个分布式总线仲裁器，其接收来自子系统的总线请求并独立地确定下一个总线主机。仲裁协议使仲裁过程能够从临界定时路径中消除，从而允许系统以给定的集成电路（IC）技术可能的最大系统时钟频率工作，以减少整体系统时钟延迟。在仲裁时钟周期期间，子系统之间的任何改变都是基于任何在仲裁时钟周期之前的时钟周期期间有效的系统总线请求，并且独立于在系统总线请求期间断言的任何系统总线请求仲裁时钟周期。此外，仲裁协议优先处理当前总线主机，即总线主机驱动系统总线。无论处理器速度如何，每个仲裁任务都在系统时钟周期内完成。因此，用于保留当前总线主机的仲裁延迟是一个系统时钟周期，而用于选择和切换总线主机的延迟是两个系统时钟周期。在此实现中，最后一个端口驱动程序是允许在时钟周期内断言总线请求的唯一子系统，并在下一个即时时钟周期内立即驱动系统总线。相反，当不是最后端口驱动器的第二子系统需要驱动非活动系统总线时，第二子系统在第一时钟周期内断言其总线请求线，并且在所有相应的总线仲裁器内进行仲裁发生在第二个时钟周期。

6. 发明授权

US5346194A Adjustable clamp 失效
标题翻译：可调夹
公开(公告)号：US5346194A
公开(公告)日：1994-09-13
申请号：US88180
申请日：1993-07-07
申请人： Louis F. Coffin, III
发明人： Louis F. Coffin, III
IPC分类号： B25B5/06 , B25B5/08 , B25B5/12 , B25B1/14
CPC分类号： B25B5/08 , B25B5/06 , B25B5/068 , B25B5/12 , B25B5/127
摘要： An improved carpenter's clamp is provided for easily securing a workpiece. The clamp has a C-shaped frame that can be mounted to a holding surface. The frame has a top and a bottom receiver aperture. A slide bar is slidably mounted in an axial direction within the top and bottom receiver apertures, and a handle is pivotally attached to the frame to provide a downward axial force to the slide bar when the handle is lowered. A toggle link is provided allowing the handle to be locked in a downward position thereby locking said slide bar in a secured position. A holding arm having a holding tip at a distal end is slidably mounted to the slide bar, and the slide bar is positioned between a pair of bias pins on the holding arm so that a workpiece can be held between the holding surface and the holding tip when a downward force is applied to the handle.
摘要翻译：提供了一种改进的木匠夹具，用于容易地固定工件。夹具具有可以安装到保持表面的C形框架。该框架具有顶部和底部接收器孔径。滑动杆在轴向方向可滑动地安装在顶部和底部接收器孔内，并且手柄枢转地附接到框架，以在手柄下降时向滑动杆提供向下的轴向力。提供了一种切换连杆，允许把手被锁定在向下的位置，从而将所述滑动杆锁定在固定位置。具有在前端的保持尖端的保持臂可滑动地安装在滑动杆上，并且滑动杆位于保持臂上的一对偏置销之间，使得工件能够保持在保持表面和保持尖端之间当向手柄施加向下的力时。

7. 发明授权

US07634171B2 PC-based personal video recorder 有权
标题翻译：基于PC的个人录像机
公开(公告)号：US07634171B2
公开(公告)日：2009-12-15
申请号：US10151676
申请日：2002-05-20
申请人： Louis F. Coffin, III
发明人： Louis F. Coffin, III
IPC分类号： H04N7/08 , G06F11/30 , G06F12/14 , H04N7/167 , H04L9/00
CPC分类号： H04N21/4143 , H04N5/76 , H04N5/775 , H04N5/781 , H04N7/167 , H04N9/8042 , H04N21/4147 , H04N21/4181 , H04N21/4334 , H04N21/4405 , H04N21/4408 , H04N2005/91364
摘要： A PC-based personal video recorder (PVR) system enables recordation of video content on a general-purpose computer in a way that the computer is unable to perceptively display the recorded content, but is able to playback and distribute the content to a decoder box (e.g., set-top box) for display on a television. In one implementation, the general-purpose computer is equipped with a personal video recorder (PVR) card having a video tuner, a network connection, and scrambling capabilities. The PVR card is configured to receive video content and produce compressed digital video. The card scrambles the video content and stores it in the computer's memory. The scrambled video content is in a form that cannot be perceptibly displayed by the computer. During playback, the PVR card retrieves the scrambled video content from the memory, descrambles it, and outputs the video content to the decoder box for playback on the television.
摘要翻译：基于PC的个人录像机（PVR）系统能够以通用计算机记录视频内容，使得计算机不能感知地显示所记录的内容，但是能够将内容回放并分发到解码器盒（例如，机顶盒），用于在电视机上显示。在一个实现中，通用计算机配备有具有视频调谐器，网络连接和加扰能力的个人录像机（PVR）卡。 PVR卡被配置为接收视频内容并产生压缩数字视频。该卡扰乱视频内容并将其存储在计算机的内存中。加扰的视频内容是不能被计算机感知地显示的形式。在播放过程中，PVR卡从存储器中取出加密的视频内容，对其进行解扰，并将视频内容输出到解码盒，以便在电视机上播放。

8. 发明授权

US07269386B2 Method and apparatus for adjusting signal component strength 有权
标题翻译：调整信号分量强度的方法和装置
公开(公告)号：US07269386B2
公开(公告)日：2007-09-11
申请号：US11027739
申请日：2004-12-30
申请人： Louis F. Coffin, III
发明人： Louis F. Coffin, III
IPC分类号： H04H1/00
CPC分类号： H04W52/42
摘要： A first signal component is received having a first signal strength and a second signal component is received having a second signal strength. A difference is identified between the first signal strength and the second signal strength. A determination is made as to whether the difference between the first signal strength and the second signal strength exceeds a threshold. If the difference between the first signal strength and the second signal strength exceeds a threshold, the first signal strength is adjusted to reduce the difference between the first signal strength and the second signal strength.
摘要翻译：接收具有第一信号强度的第一信号分量，并且接收具有第二信号强度的第二信号分量。在第一信号强度和第二信号强度之间识别出差异。确定第一信号强度和第二信号强度之间的差是否超过阈值。如果第一信号强度和第二信号强度之间的差超过阈值，则调整第一信号强度以减小第一信号强度和第二信号强度之间的差。

9. 发明授权

US5737755A System level mechanism for invalidating data stored in the external cache of a processor in a computer system 失效
标题翻译：用于使存储在计算机系统中的处理器的外部高速缓存中的数据无效的系统级机制
公开(公告)号：US5737755A
公开(公告)日：1998-04-07
申请号：US797995
申请日：1997-02-12
申请人： Zahir Ebrahim , Satyanarayana Nishtala , William Van Loo , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III
发明人： Zahir Ebrahim , Satyanarayana Nishtala , William Van Loo , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0808 , G06F12/0817
摘要： A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.
摘要翻译：公开了一种计算机系统，其包括存储器子系统和具有外部高速缓存的处理器子系统和用于使处理器子系统中的高速缓存的数据块无效并用于减少假无效操作的外部机制。处理器子系统向指定数据块的存储器子系统发出写入无效消息，并且包括指示数据块是否存在于外部高速缓存中的无效咨询指示。无效咨询指示确定存储器子系统是否向处理器子系统返回无效消息以用于写入无效操作。

10. 发明授权

US5692197A Method and apparatus for reducing power consumption in a computer network without sacrificing performance 失效
标题翻译：用于在不牺牲性能的情况下降低计算机网络中的功耗的方法和装置
公开(公告)号：US5692197A
公开(公告)日：1997-11-25
申请号：US414879
申请日：1995-03-31
申请人： Charles E. Narad , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin B. Normoyle , Louis F. Coffin, III , Leslie Kohn
发明人： Charles E. Narad , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin B. Normoyle , Louis F. Coffin, III , Leslie Kohn
IPC分类号： G06F1/32 , G06F15/16 , G06F15/177
CPC分类号： G06F1/3209
摘要： A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independently initiating a transition into a power-conserving mode, i.e., a "sleep" state, while keeping its network interface "alive" and fully operational. Subsequently, each computer system can independently transition back into fully operational state, i.e., an "awake" state, when triggered by either a deterministic or an asynchronous event. As a result, the sleep states of the computer systems are transparent to the computer network. Deterministic events are events triggered internally by a computer system, e.g., an internal timer waking the computer system up at midnight to perform housekeeping chores such as daily tape backups. Conversely, the source of asynchronous events are external in nature and include input/output (I/O) activity. The illusion of the entire network being always fully operational is possible because the system controllers, the interconnects and network interfaces of each computer system remain fully operational while selected modules and peripheral devices are powered down. As a result, each computer system is able to rapidly awake from sleep state in response to stimuli by powering down selected modules thereby accomplishing power conservation without requiring a static shut down of the computer network, i.e., without the overall performance and response of the computer network.
摘要翻译：一种用于主动管理计算机网络的整体功耗的方法和装置，其包括彼此互连的多个计算机系统。反过来，每个计算机系统具有一个或多个模块。计算机网络的每个计算机系统能够独立地启动向省电模式转变，即“休眠”状态，同时保持其网络接口“活着”并且完全可操作。随后，当由确定性或异步事件触发时，每个计算机系统可以独立地转换回完全操作状态，即“清醒”状态。因此，计算机系统的睡眠状态对于计算机网络是透明的。确定性事件是由计算机系统在内部触发的事件，例如内部定时器在午夜唤醒计算机系统以执行诸如日常磁带备份的家务杂务。相反，异步事件的来源本质上是外部的，包括输入/输出（I / O）活动。整个网络的错觉始终是完全可操作的，因为每个计算机系统的系统控制器，互连和网络接口在选定的模块和外围设备关闭电源时保持完全可操作。因此，每个计算机系统能够通过断电所选择的模块来迅速地从睡眠状态唤醒，从而实现功率节省，而不需要静态关闭计算机网络，即没有计算机的整体性能和响应网络。

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