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1. 发明申请

US20050055499A1 Circulator chain memory command and address bus topology 有权
标题翻译：循环链存储器命令和地址总线拓扑
公开(公告)号：US20050055499A1
公开(公告)日：2005-03-10
申请号：US10658883
申请日：2003-09-09
申请人： Michael Leddige , James McCall
发明人： Michael Leddige , James McCall
IPC分类号： G11C5/00 , G11C5/06 , G11C8/12 , G06F12/00
CPC分类号： G11C8/12 , G11C5/063 , G11C7/1066
摘要： Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA signal is routed to a first of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal is then divided into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM. The CA signal components are then recombined and routed to the second DIMM. The recombined CA signal is then divided again into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM and the CA signal components are then recombined. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM.
摘要翻译：本发明的实施例提供了一种存储器命令和地址（CA）总线架构，其可以适应具有降低的信号劣化的较高CA数据输出频率。对于本发明的一个实施例，CA信号被路由到两DIMM /通道存储器总线设计的两个双列直插存储器模块（DIMM）中的第一个。然后将CA信号分成组件，每个CA信号分量通过一组第一DIMM上的动态随机存取存储器（DRAM）芯片串行路由。然后将CA信号组件重新组合并路由到第二个DIMM。然后将重新组合的CA信号再划分成组件，每个CA信号分量被顺序地路由在第一DIMM上的一组动态随机存取存储器（DRAM）芯片，然后CA信号分量被重新组合。在一个实施例中，在路由每个DRAM之后，CA信号在DIMM上终止。

2. 发明申请

US20050033905A1 Split T-chain memory command and address bus topology 有权
标题翻译：分割T链存储器命令和地址总线拓扑
公开(公告)号：US20050033905A1
公开(公告)日：2005-02-10
申请号：US10638069
申请日：2003-08-08
申请人： Michael Leddige , James McCall
发明人： Michael Leddige , James McCall
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C5/00
CPC分类号： G06F13/4239 , G11C5/04
摘要： Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.
摘要翻译：本发明的实施例提供了一种存储器命令和地址（CA）总线架构，其可以适应具有降低的信号劣化的较高CA数据输出频率。对于本发明的一个实施例，CA在主板上被划分，并且CA信号分量被路由到两个DIMM /通道存储器总线设计的两个双列直插式存储器模块（DIMM）中的每一个。然后，每个DIMM上的CA信号分量依次通过相应DIMM上的每个动态随机存取存储器（DRAM）芯片。在一个实施例中，在路由每个DRAM之后，CA信号在DIMM上终止。在替代实施例中，CA信号在每个相应的DIMM的最后一个DRAM处终止在管芯上。

3. 发明申请

US20060291572A1 Method and system for a configurable Vcc reference and Vss reference differential current mode transmitter 有权
标题翻译：可配置Vcc参考和Vss参考差分电流模式发送器的方法和系统
公开(公告)号：US20060291572A1
公开(公告)日：2006-12-28
申请号：US11168255
申请日：2005-06-27
申请人： Hing To , James McCall , Michael Sandhinti
发明人： Hing To , James McCall , Michael Sandhinti
IPC分类号： H04B3/00 , H04B1/38
CPC分类号： H03F3/45179 , H03F3/45237 , H03F3/72
摘要： A method and system for a configurable Vcc reference and Vss reference differential current mode transmitter is described. The system includes a Vss reference differential current mode driver, a Vcc reference differential current mode driver coupled to the Vss reference current mode driver, and a controller circuit coupled to the Vss reference differential current mode driver and the Vcc reference differential current mode driver to select between the Vss reference differential current mode driver and the Vcc reference differential current mode driver based on a type of transmission interface.
摘要翻译：描述了可配置Vcc参考和Vss参考差分电流模式发射机的方法和系统。该系统包括Vss参考差分电流模式驱动器，耦合到Vss参考电流模式驱动器的Vcc参考差分电流模式驱动器，以及耦合到Vss参考差分电流模式驱动器和Vcc参考差分电流模式驱动器的控制器电路，以选择在Vss参考差动电流模式驱动器和Vcc参考差动电流模式驱动器之间基于一种传输接口。

4. 发明申请

US20060284733A1 Initiation of differential link retraining upon temperature excursion 有权
标题翻译：在温度偏移时启动差动连杆再培训
公开(公告)号：US20060284733A1
公开(公告)日：2006-12-21
申请号：US11156837
申请日：2005-06-20
申请人： James McCall , Klaus Ruff , David Shykind
发明人： James McCall , Klaus Ruff , David Shykind
IPC分类号： G08B17/00
CPC分类号： G11C7/22 , G06F13/1694 , G11C7/04 , G11C2207/2254
摘要： A method includes detecting a change in temperature in an integrated circuit that is coupled to a differential communication link, and responding to the detected change in temperature by initiating a retraining process for the differential communication link.
摘要翻译：一种方法包括检测耦合到差分通信链路的集成电路中的温度变化，以及通过启动用于差分通信链路的再培训处理来响应于检测到的温度变化。

5. 发明申请

US20140150257A1 METHOD OF MANUFACTURING A CIRCUIT BOARD 审中-公开
标题翻译：制造电路板的方法
公开(公告)号：US20140150257A1
公开(公告)日：2014-06-05
申请号：US14173554
申请日：2014-02-05
申请人： David Shykind , James McCall
发明人： David Shykind , James McCall
IPC分类号： H05K3/10
CPC分类号： H05K3/10 , H05K1/0216 , H05K1/0245 , H05K1/0248 , H05K1/0366 , H05K3/0052 , H05K2201/0187 , H05K2201/029 , H05K2201/09236 , H05K2201/09972 , H05K2203/1554 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49798 , Y10T428/24058 , Y10T428/24917 , Y10T428/249935 , Y10T428/24994 , Y10T428/249943 , Y10T428/249946 , Y10T442/2926 , Y10T442/2992 , Y10T442/3065
摘要： A method of manufacturing a circuit board is described herein. The method may include adding a resin, forming first and second fiberglass fibers, and forming first and second signal line traces capable of transmitting electrical signals. In some examples, a ratio between fiberglass and resin material near the first signal line trace is similar to a ratio between fiberglass and resin material near the second signal line trace. In some examples, the first and second fiberglass fibers diagonally cross near the first and second signal line traces. In some examples, the first and second fiberglass fibers cross near the first and second signal line traces in a zig-zag pattern.
摘要翻译：这里描述了制造电路板的方法。该方法可以包括添加树脂，形成第一和第二玻璃纤维纤维，以及形成能够传输电信号的第一和第二信号线迹线。在一些实例中，第一信号线迹线附近的玻璃纤维和树脂材料之间的比率类似于第二信号线迹线附近的玻璃纤维和树脂材料之间的比率。在一些示例中，第一和第二玻璃纤维光纤在第一和第二信号线迹线附近对角地交叉。在一些示例中，第一和第二玻璃纤维纤维以锯齿形图案在第一和第二信号线迹线附近交叉。

6. 发明申请

US20070169341A1 Circuit board design 有权
标题翻译：电路板设计
公开(公告)号：US20070169341A1
公开(公告)日：2007-07-26
申请号：US11727279
申请日：2007-03-26
申请人： James McCall , David Shykind
发明人： James McCall , David Shykind
IPC分类号： H05K3/20 , B23P17/00
CPC分类号： H05K3/10 , H05K1/0216 , H05K1/0245 , H05K1/0248 , H05K1/0366 , H05K3/0052 , H05K2201/0187 , H05K2201/029 , H05K2201/09236 , H05K2201/09972 , H05K2203/1554 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49798 , Y10T428/24058 , Y10T428/24917 , Y10T428/249935 , Y10T428/24994 , Y10T428/249943 , Y10T428/249946 , Y10T442/2926 , Y10T442/2992 , Y10T442/3065
摘要： A circuit board is described where the fiberglass fiber pattern as been modified than what is found in conventional FR4 circuit boards. In one embodiment, the sets of fiberglass fibers are disposed in a zig-zag or herringbone manner. In one use, when a pair of conductors are disposed onto or into the board, the material surrounding a first conductor tends to be similar to the material surrounding a second conductor. Doing so may reduce differential to common mode conversion between the conductors.
摘要翻译：描述了电路板，其中比常规FR4电路板中发现的玻璃纤维模式被修改。在一个实施例中，玻璃纤维组织以锯齿形或人字形方式设置。在一种用途中，当一对导体设置在板上或其中时，围绕第一导体的材料倾向于类似于围绕第二导体的材料。这样做可能会降低导体间的共模转换。

7. 发明申请

US20070002676A1 Buffered continuous multi-drop clock ring 审中-公开
标题翻译：缓冲连续多点钟环
公开(公告)号：US20070002676A1
公开(公告)日：2007-01-04
申请号：US11516824
申请日：2006-09-06
申请人： James McCall , Clinton Walker
发明人： James McCall , Clinton Walker
IPC分类号： G11C8/00
CPC分类号： G06F1/10 , G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A method, system and apparatus to distribute a clock signal among a plurality of memory units in a memory architecture. A buffer chip is coupled to a plurality of memory units each by a point to point link. The buffer chip includes a clock generator to generate a continuous free running clock that may be passed serially through a subset of memory units in the architecture. Sending of data is delayed over the point to point links based on proximity of the memory units to the buffer chip to accommodate delay in the multidrop clock signal.
摘要翻译：一种在存储器架构中的多个存储器单元之间分配时钟信号的方法，系统和装置。缓冲器芯片通过点对点链接耦合到多个存储器单元。缓冲器芯片包括一个时钟发生器，用于产生一个连续的自由运行时钟，该时钟可以串行地通过架构中存储器单元的子集。基于存储器单元与缓冲器芯片的接近度，数据的发送在点对点链路上被延迟以适应多点时钟信号的延迟。

8. 发明申请

US20060067398A1 Adaptive delay base loss equalization 有权
公开(公告)号：US20060067398A1
公开(公告)日：2006-03-30
申请号：US10956426
申请日：2004-09-30
申请人： James McCall , Klaus Ruff , David Shykind , Santanu Chaudhuri
发明人： James McCall , Klaus Ruff , David Shykind , Santanu Chaudhuri
IPC分类号： H03K5/159
CPC分类号： H04L25/0224 , H04L7/0008 , H04L25/03878 , H04L2025/03751
摘要： A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a responder on channel to be equalized and begins a count. A responder responds with an EIS. When the initiator receives the response EIS the count is terminated. The count, which constitutes a measure of delay in the channel, may be used to determine desirable equalization parameters for the channel.

9. 发明申请

US20060288132A1 Memory single-to-multi load repeater architecture 审中-公开
标题翻译：内存单对多中继器架构
公开(公告)号：US20060288132A1
公开(公告)日：2006-12-21
申请号：US11141668
申请日：2005-05-31
申请人： James McCall , Pete Vogt
发明人： James McCall , Pete Vogt
IPC分类号： G06F13/00
CPC分类号： G06F13/4234 , G06F13/4095
摘要： According to some embodiments, data is transmitted from a host to a first memory unit in a group of memory units. The data may then be repeated from the first memory unit to another memory unit in the group.
摘要翻译：根据一些实施例，数据从主机发送到一组存储器单元中的第一存储器单元。然后可以将数据从第一存储器单元重复到组中的另一个存储器单元。

10. 发明申请

US20060285847A1 Systems with variable link widths 失效
标题翻译：具有可变链路宽度的系统
公开(公告)号：US20060285847A1
公开(公告)日：2006-12-21
申请号：US11155857
申请日：2005-06-17
申请人： James McCall , Bruce Christenson
发明人： James McCall , Bruce Christenson
IPC分类号： H04J14/00
CPC分类号： G06F13/4068 , Y02D10/14 , Y02D10/151
摘要： In some embodiments, a chip includes transmitters and receivers, and control circuitry. The control circuitry to cause some of the transmitters and receivers to be inoperative in response to an estimated activity level being in a first range, while others of the transmitters and receivers remain operative. Other embodiments are described and/or claimed.
摘要翻译：在一些实施例中，芯片包括发射器和接收器以及控制电路。所述控制电路使得一些发射器和接收器响应于估计的活动电平处于第一范围而不起作用，而发射器和接收器中的另一个保持有效。描述和/或要求保护其他实施例。

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