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1. 发明申请

US20060291572A1 Method and system for a configurable Vcc reference and Vss reference differential current mode transmitter 有权
标题翻译：可配置Vcc参考和Vss参考差分电流模式发送器的方法和系统
公开(公告)号：US20060291572A1
公开(公告)日：2006-12-28
申请号：US11168255
申请日：2005-06-27
申请人： Hing To , James McCall , Michael Sandhinti
发明人： Hing To , James McCall , Michael Sandhinti
IPC分类号： H04B3/00 , H04B1/38
CPC分类号： H03F3/45179 , H03F3/45237 , H03F3/72
摘要： A method and system for a configurable Vcc reference and Vss reference differential current mode transmitter is described. The system includes a Vss reference differential current mode driver, a Vcc reference differential current mode driver coupled to the Vss reference current mode driver, and a controller circuit coupled to the Vss reference differential current mode driver and the Vcc reference differential current mode driver to select between the Vss reference differential current mode driver and the Vcc reference differential current mode driver based on a type of transmission interface.
摘要翻译：描述了可配置Vcc参考和Vss参考差分电流模式发射机的方法和系统。该系统包括Vss参考差分电流模式驱动器，耦合到Vss参考电流模式驱动器的Vcc参考差分电流模式驱动器，以及耦合到Vss参考差分电流模式驱动器和Vcc参考差分电流模式驱动器的控制器电路，以选择在Vss参考差动电流模式驱动器和Vcc参考差动电流模式驱动器之间基于一种传输接口。

2. 发明申请

US20060245519A1 Calibrating integrating receivers for source synchronous protocol 有权
标题翻译：校准源同步协议的集成接收器
公开(公告)号：US20060245519A1
公开(公告)日：2006-11-02
申请号：US11118228
申请日：2005-04-28
申请人： Roger Cheng , Harishankar Sridharan , Navneet Dour , Hing To
发明人： Roger Cheng , Harishankar Sridharan , Navneet Dour , Hing To
IPC分类号： H04L27/00
CPC分类号： H04L25/20
摘要： An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver calibration pulse generator generates an IR calibration pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.
摘要翻译：本发明的实施例是校准积分接收器的技术。延迟校准电路校准延迟元件链的调整代码，并且至少定位用于为积分接收器定义积分窗口的积分选通脉冲。积分接收器校准脉冲发生器从至少积分选通器产生IR校准脉冲。校准控制器控制校准调整代码和至少积分选通脉冲的定位。

3. 发明申请

US20050195677A1 Method and apparatus for optimizing timing for a multi-drop bus 有权
公开(公告)号：US20050195677A1
公开(公告)日：2005-09-08
申请号：US11121789
申请日：2005-05-04
申请人： Joseph Salmon , Hing To
发明人： Joseph Salmon , Hing To
IPC分类号： G06F11/00 , G06F13/42 , G11C8/00 , G11C29/50 , H04J3/06 , H04L1/24
CPC分类号： G11C29/50 , G06F13/4243 , G11C29/028 , G11C29/50012
摘要： A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

4. 发明授权

US07388795B1 Modular memory controller clocking architecture 有权
标题翻译：模块化内存控制器时钟架构
公开(公告)号：US07388795B1
公开(公告)日：2008-06-17
申请号：US11647656
申请日：2006-12-28
申请人： Hing To , Mamun Ur Rashid
发明人： Hing To , Mamun Ur Rashid
IPC分类号： G11C7/00
CPC分类号： H03L7/0812 , H03L7/0805
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes a phase locked loop (PLL) to generate a differential reference clock and a first clocking component coupled to the PLL. The first clocking component includes a first delay locked loop (DLL) to receive the reference clock and to generate transmit and receive delay de-skew clock signals, a first set of phase interpolators to provide data transmit de-skewing and a first set of slave delay lines to provide data receive de-skewing.
摘要翻译：根据一个实施例，公开了一种存储器控制器。存储器控制器包括产生差分参考时钟的锁相环（PLL）和耦合到PLL的第一时钟元件。第一时钟元件包括接收参考时钟并产生发射和接收延迟去偏移时钟信号的第一延迟锁定环路（DLL），提供数据发射去偏移的第一组相位内插器和第一组从站延迟线提供数据接收去偏移。

5. 发明申请

US20070079034A1 Method and apparatus for power efficient and scalable memory interface 有权
公开(公告)号：US20070079034A1
公开(公告)日：2007-04-05
申请号：US11518297
申请日：2006-09-08
申请人： Hing To , Joe Salmon
发明人： Hing To , Joe Salmon
IPC分类号： G06F13/42
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： Transmission of digital signals across a bus between an electronic device having a transmitter and another electronic device having a receiver with termination for both the transmitter and receiver being referenced to ground, such that the electronic device having the transmitter and the other electronic device having the receiver are able to be powered with differing decoupled voltages, such that the voltage employed by the electronic device having the transmitter is able to be lower than the voltage employed by the other electronic device having the receiver, and wherein the electronic device having the transmitter may transmit addresses and/or commands to the other device having the receiver using single-ended signaling, while both electronic devices may exchange data using differential signaling.

6. 发明申请

US20070006011A1 Nibble de-skew method, apparatus, and system 有权
标题翻译：半字节去偏移方法，装置和系统
公开(公告)号：US20070006011A1
公开(公告)日：2007-01-04
申请号：US11172149
申请日：2005-06-30
申请人： Aaron Martin , Hing To , Mamun Rashid , Joe Salmon
发明人： Aaron Martin , Hing To , Mamun Rashid , Joe Salmon
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F13/40 , G06F13/4243 , G11C7/1033
摘要： De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.
摘要翻译：以半字节为单位执行去偏移，其中半字节不限于四位。

7. 发明申请

US20080162977A1 MODULAR MEMORY CONTROLLER CLOCKING ARCHITECTURE 有权
标题翻译：模块化记忆控制器时钟结构
公开(公告)号：US20080162977A1
公开(公告)日：2008-07-03
申请号：US11647656
申请日：2006-12-28
申请人： Hing To , Mamun Ur Rashid
发明人： Hing To , Mamun Ur Rashid
IPC分类号： G06F1/04
CPC分类号： H03L7/0812 , H03L7/0805
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes a phase locked loop (PLL) to generate a differential reference clock and a first clocking component coupled to the PLL. The first clocking component includes a first delay locked loop (DLL) to receive the reference clock and to generate transmit and receive delay de-skew clock signals, a first set of phase interpolators to provide data transmit de-skewing and a first set of slave delay lines to provide data receive de-skewing.
摘要翻译：根据一个实施例，公开了一种存储器控制器。存储器控制器包括产生差分参考时钟的锁相环（PLL）和耦合到PLL的第一时钟元件。第一时钟元件包括接收参考时钟并产生发射和接收延迟去偏移时钟信号的第一延迟锁定环路（DLL），提供数据发射去偏移的第一组相位内插器和第一组从站延迟线提供数据接收去偏移。

8. 发明申请

US20060101167A1 Method and apparatus for power efficient and scalable memory interface 有权
标题翻译：用于功率高效和可扩展的存储器接口的方法和装置
公开(公告)号：US20060101167A1
公开(公告)日：2006-05-11
申请号：US10982632
申请日：2004-11-05
申请人： Hing To , Joe Salmon
发明人： Hing To , Joe Salmon
IPC分类号： G06F13/28
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： Transmission of digital signals across a bus between an electronic device having a transmitter and another electronic device having a receiver with termination for both the transmitter and receiver being referenced to ground, such that the electronic device having the transmitter and the other electronic device having the receiver are able to be powered with differing decoupled voltages, such that the voltage employed by the electronic device having the transmitter is able to be lower than the voltage employed by the other electronic device having the receiver, and wherein the electronic device having the transmitter may transmit addresses and/or commands to the other device having the receiver using single-ended signaling, while both electronic devices may exchange data using differential signaling.
摘要翻译：在具有发射机的电子设备和具有用于发射机和接收机的终端的接收机的另一个电子设备之间的总线上的数字信号的传输被称为接地，使得具有发射机和其他电子设备的电子设备具有接收机能够用不同的解耦电压供电，使得具有发射器的电子设备所使用的电压能够低于具有接收器的其他电子设备使用的电压，并且其中具有发射器的电子设备可以传输地址和/或命令到具有接收机使用单端信令的另一设备，而两个电子设备可以使用差分信令交换数据。

9. 发明申请

US20060067155A1 Latency normalization by balancing early and late clocks 有权
标题翻译：通过平衡早期和晚期时钟的延迟归一化
公开(公告)号：US20060067155A1
公开(公告)日：2006-03-30
申请号：US10949053
申请日：2004-09-24
申请人： Hing To , Joe Salmon , Mamun Rashid
发明人： Hing To , Joe Salmon , Mamun Rashid
IPC分类号： G11C8/00
CPC分类号： G06F1/10
摘要： A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，该方法包括将早期时钟信号和后期时钟信号输入到存储器件，并通过对早期时钟信号和后期时钟信号进行平均来产生存储器件的平均时钟信号。

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