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1. 发明授权

US08813012B2 Self-aligned via interconnect using relaxed patterning exposure 有权
标题翻译：通过使用松弛图案曝光的互连自对准
公开(公告)号：US08813012B2
公开(公告)日：2014-08-19
申请号：US13550460
申请日：2012-07-16
申请人： Michael L. Rieger , Victor Moroz
发明人： Michael L. Rieger , Victor Moroz
IPC分类号： G06F17/50
CPC分类号： H01L23/5226 , G06F17/5072 , H01L21/76816 , H01L21/76877 , H01L23/53228 , H01L23/53295 , H01L23/5384 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.
摘要翻译：通过使用松弛图案曝光的互连自对准。根据第一方法实施例，一种用于控制用于设计集成电路的物理特征的计算机辅助设计（CAD）系统的方法包括：访问用于第一金属层上的第一金属迹线的第一图案，访问用于第二金属层的第二图案垂直于第一金属层的第二金属层上的金属迹线，并且访问第一和第二金属迹线之间的预期互连的精确图案。操作预定互连的精确模式以形成指示允许通孔的多个通用区域的不精确的通孔图案。通过图案的不精确性用于集成电路制造过程中，与形成第一和第二金属层的操作一起形成用于互连预期互连的多个自对准通孔。

2. 发明申请

US20140015135A1 SELF-ALIGNED VIA INTERCONNECT USING RELAXED PATTERNING EXPOSURE 有权
标题翻译：通过使用放松的图案曝光进行互连时自动对齐
公开(公告)号：US20140015135A1
公开(公告)日：2014-01-16
申请号：US13550460
申请日：2012-07-16
申请人： Michael L. Rieger , Victor Moroz
发明人： Michael L. Rieger , Victor Moroz
IPC分类号： H01L21/768 , H01L23/538 , G06F17/50
CPC分类号： H01L23/5226 , G06F17/5072 , H01L21/76816 , H01L21/76877 , H01L23/53228 , H01L23/53295 , H01L23/5384 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.
摘要翻译：通过使用松弛图案曝光的互连自对准。根据第一方法实施例，一种用于控制用于设计集成电路的物理特征的计算机辅助设计（CAD）系统的方法包括：访问用于第一金属层上的第一金属迹线的第一图案，访问用于第二金属层的第二图案垂直于第一金属层的第二金属层上的金属迹线，并且访问第一和第二金属迹线之间的预期互连的精确图案。操作预定互连的精确模式以形成指示允许通孔的多个通用区域的不精确的通孔图案。通过图案的不精确性用于集成电路制造过程中，与形成第一和第二金属层的操作一起形成用于互连预期互连的多个自对准通孔。

3. 发明授权

US09917018B2 Method and apparatus with channel stop doped devices 有权
公开(公告)号：US09917018B2
公开(公告)日：2018-03-13
申请号：US13693906
申请日：2012-12-04
申请人： Victor Moroz
发明人： Victor Moroz
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/762 , G06F17/50
CPC分类号： H01L21/823878 , G06F17/5068 , H01L21/76213 , H01L21/823821
摘要： Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.

4. 发明申请

US20140154855A1 METHOD AND APPARATUS WITH CHANNEL STOP DOPED DEVICES 有权
标题翻译：具有通道停止装置的方法和装置
公开(公告)号：US20140154855A1
公开(公告)日：2014-06-05
申请号：US13693906
申请日：2012-12-04
申请人： Victor Moroz
发明人： Victor Moroz
IPC分类号： H01L29/66 , G06F17/50
CPC分类号： H01L21/823878 , G06F17/5068 , H01L21/76213 , H01L21/823821
摘要： Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.
摘要翻译：方法和装置涉及用掺杂剂注入半导体衬底的表面，将未掺杂的半导体材料直接注入到注入掺杂剂的表面上，以及在未掺杂的半导体材料中制造具有晶体管沟道的晶体管，使得晶体管的晶体管沟道在整个集成电路的制造过程中保持未掺杂。

5. 发明授权

US08723268B2 N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch 有权
标题翻译： N沟道和P沟道端到端finFET单元架构，具有放宽的栅极间距
公开(公告)号：US08723268B2
公开(公告)日：2014-05-13
申请号：US13495810
申请日：2012-06-13
申请人： Victor Moroz , Deepak D. Sherlekar
发明人： Victor Moroz , Deepak D. Sherlekar
IPC分类号： H01L29/76
CPC分类号： H01L27/0924 , G06F17/5068 , H01L21/823821 , H01L23/528 , H01L27/0207 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.
摘要翻译： finFET块结构使用端到端finFET块，其中鳍长度至少为接触间距的两倍，由此在给定半导体鳍片的近端和远端上存在用于层间连接器的足够空间，并在给定半导体鳍片上的栅极元件上。具有第一导电类型的第一组半导体鳍片和具有第二导电类型的第二组半导体鳍片可以端对齐地对准。层间连接器可以对准连接到栅极元件的相应半导体鳍片上。

6. 发明授权

US08686512B2 Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance 有权
标题翻译：提高晶体管通道，减少浅沟槽隔离对晶体管性能的影响
公开(公告)号：US08686512B2
公开(公告)日：2014-04-01
申请号：US13221747
申请日：2011-08-30
申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
摘要翻译：粗略描述，晶体管沟道区域在某些相邻STI区域的水平上升高。优选地，与扩散区横向相邻的STI区域被抑制，与N沟道扩散区域纵向相邻的STI区也是如此。优选地，与P沟道扩散纵向相邻的STI区域不被抑制; 优选地，它们具有至少与扩散区域相同的高度。

7. 发明授权

US08354736B2 Reclaiming usable integrated circuit chip area near through-silicon vias 有权
标题翻译：回收通过硅通孔的可用集成电路芯片区域
公开(公告)号：US08354736B2
公开(公告)日：2013-01-15
申请号：US12687358
申请日：2010-01-14
申请人： Victor Moroz
发明人： Victor Moroz
IPC分类号： H01L29/40
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via in the silicon wafer. SiO2 is then formed on the inside surface of the SiGe, and metal is formed down the center. The stresses introduce by the SiGe tend to counteract the stresses introduced by the metal, thereby reducing or eliminating undesirable stress in the silicon and permitting the placement of transistors in close proximity to the TSV.
摘要翻译：粗略地描述，集成电路器件包括：衬底，其包括穿过其中的通孔，通孔中的应变导电的第一材料，倾向于将第一应力引入衬底的第一材料和通孔中的应变的第二材料，第二材料倾向于将至少部分地抵消第一应力的第二应力引入衬底。在一个实施例中，SiGe在硅晶片中的通孔的内侧壁上外延生长。然后在SiGe的内表面上形成SiO 2，并且在中心形成金属。由SiGe引入的应力倾向于抵消由金属引入的应力，从而减少或消除硅中的不期望的应力，并允许将晶体管放置在TSV附近。

8. 发明授权

US08219961B2 Method for compensation of process-induced performance variation in a MOSFET integrated circuit 有权
标题翻译： MOSFET集成电路中过程引起的性能变化的补偿方法
公开(公告)号：US08219961B2
公开(公告)日：2012-07-10
申请号：US13112837
申请日：2011-05-20
申请人： Victor Moroz , Dipankar Pramanik , Kishore Singhal , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Kishore Singhal , Xi-Wei Lin
IPC分类号： G06F9/455 , G06F17/50 , G06F11/22
CPC分类号： G06F17/5068 , G06F17/5036
摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
摘要翻译：用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。该方法的第一步是从阵列中选择一个用于分析的晶体管。该方法根据需要在阵列的晶体管之间循环。接下来分析所选晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定由布局邻域引起的驱动电流变化。该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

9. 发明授权

US07960232B2 Methods of designing an integrated circuit on corrugated substrate 有权
标题翻译：在瓦楞纸基板上设计集成电路的方法
公开(公告)号：US07960232B2
公开(公告)日：2011-06-14
申请号：US12410428
申请日：2009-03-24
申请人： Tsu-Jae King , Victor Moroz
发明人： Tsu-Jae King , Victor Moroz
IPC分类号： H01L21/336
CPC分类号： H01L29/34 , H01L21/78 , H01L21/84 , H01L23/544 , H01L27/0886 , H01L27/1203 , H01L29/0653 , H01L29/1054 , H01L29/165 , H01L29/66795 , H01L29/7843 , H01L29/785 , H01L2223/5446 , Y10S438/974
摘要： By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.
摘要翻译：通过在具有预先存在的半导体材料的脊（即，“波纹状基板”）的基板上形成MOSFET，可以克服与常规半导体制造工艺相关的分辨率限制，并且可以可靠地实现高性能的低功率晶体管，重复生产。在实际的器件形成之前形成波纹状衬底可以使用通常不适用于器件生产的高精度技术来产生波纹衬底上的脊。随后将高精度脊结合到其沟道区中的MOSFET通常将显示出比使用不能提供相同程度的图案精度的基于光刻技术形成的类似的MOSFET更精确和更少可变的性能。附加的性能增强技术，例如脉冲形掺杂和“包裹”栅极可以与分段通道区域一起使用，以进一步提高器件性能。

10. 发明申请

US20100187609A1 BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS 审中-公开
标题翻译：提高非矩形通道的晶体管性能
公开(公告)号：US20100187609A1
公开(公告)日：2010-07-29
申请号：US12390338
申请日：2009-02-20
申请人： Victor Moroz , Munkang Choi , Xi-Wei Lin
发明人： Victor Moroz , Munkang Choi , Xi-Wei Lin
IPC分类号： H01L27/088 , G06F17/50 , G03F1/00
CPC分类号： G06F17/5072 , H01L21/266 , H01L27/0207 , H01L29/1033 , H01L29/41758
摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.
摘要翻译：粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

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