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1. 发明授权

US06943055B2 Method and apparatus for detecting backside contamination during fabrication of a semiconductor wafer 失效
标题翻译：用于在制造半导体晶片期间检测背面污染的方法和装置
公开(公告)号：US06943055B2
公开(公告)日：2005-09-13
申请号：US10628601
申请日：2003-07-28
申请人： Michael J. Berman , George E. Bailey , Rennie G. Barber
发明人： Michael J. Berman , George E. Bailey , Rennie G. Barber
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L21/67259
摘要： A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
摘要翻译：检测半导体晶片背面的污染物的方法包括以下步骤：将晶片的背面与污染物传感器的检测表面接触，并检测污染物传感器的检测表面的变形。污染物传感器可以结合到诸如晶片处理装置的制造装置中，或者可以用于独立装置的构造。还公开了一种用于检测半导体晶片背面污染的装置。

2. 发明授权

US06627466B1 Method and apparatus for detecting backside contamination during fabrication of a semiconductor wafer 失效
标题翻译：用于在制造半导体晶片期间检测背面污染的方法和装置
公开(公告)号：US06627466B1
公开(公告)日：2003-09-30
申请号：US10138742
申请日：2002-05-03
申请人： Michael J. Berman , George E. Bailey , Rennie G. Barber
发明人： Michael J. Berman , George E. Bailey , Rennie G. Barber
IPC分类号： H01L2166
CPC分类号： H01L21/67259
摘要： A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
摘要翻译：检测半导体晶片背面的污染物的方法包括以下步骤：将晶片的背面与污染物传感器的检测表面接触，并检测污染物传感器的检测表面的变形。污染物传感器可以结合到诸如晶片处理装置的制造装置中，或者可以用于独立装置的构造。还公开了一种用于检测半导体晶片背面污染的装置。

3. 发明授权

US06898064B1 System and method for optimizing the electrostatic removal of a workpiece from a chuck 失效
标题翻译：用于从卡盘优化工件的静电去除的系统和方法
公开(公告)号：US06898064B1
公开(公告)日：2005-05-24
申请号：US09942220
申请日：2001-08-29
申请人： Michael J. Berman , Rennie G. Barber
发明人： Michael J. Berman , Rennie G. Barber
IPC分类号： H01L21/683 , H01T23/00
CPC分类号： H01L21/6831
摘要： A system and method are presented for neutralizing the electric charge binding a semiconductor wafer to an electrostatic chuck. When processing of a semiconductor wafer has been completed, lifter pins, driven by solenoids or pistons, are provided within the chuck to remove the wafer. However, if the electrostatic force has not been completely dissipated, the pins may have to push very hard against the wafer to dislodge it. When this occurs, the wafer may be violently displaced from the chuck, resulting in misplacement of the wafer, or even damage. A system and method are disclosed herein for completely neutralizing the electrostatic charge before removal of the wafer is attempted. Neutralization is detected as the point at which the electrostatic force opposing the lifting mechanism reaches a minimum.
摘要翻译：提出了一种用于中和将半导体晶片结合到静电卡盘的电荷的系统和方法。当半导体晶片的处理已经完成时，由电磁线圈或活塞驱动的升降器销设置在卡盘内以移除晶片。然而，如果静电力没有被完全消散，则针可能必须非常坚硬地推向晶片以将其移开。当这种情况发生时，晶片可能会从卡盘猛烈移位，导致晶片错位，甚至损坏。本文公开的系统和方法用于在尝试去除晶片之前完全中和静电电荷。检测到中和作为与提升机构相对的静电力达到最小的点。

4. 发明授权

US06849936B1 System and method for using film deposition techniques to provide an antenna within an integrated circuit package 有权
标题翻译：使用成膜技术在集成电路封装内提供天线的系统和方法
公开(公告)号：US06849936B1
公开(公告)日：2005-02-01
申请号：US10254473
申请日：2002-09-25
申请人： Michael J. Berman , Rennie G. Barber
发明人： Michael J. Berman , Rennie G. Barber
IPC分类号： H01L23/02 , H01L23/552 , H01L23/58 , H01L23/66 , H01Q1/22 , H01Q9/30 , H01Q23/00
CPC分类号： H01Q1/2283 , H01L23/552 , H01L23/66 , H01L24/19 , H01L2223/6677 , H01L2924/12042 , H01L2924/14 , H01L2924/16152 , H01Q1/22 , H01Q9/30 , H01Q23/00 , H01L2924/00
摘要： An integrated circuit package comprises a cavity for housing an integrated circuit (IC) and an antenna provided as part of the package that is located substantially outside the cavity. The antenna may be located on the floor of the IC package that lies in the region outside of the IC cavity. Alternatively, the antenna may be located on the upper or lower surface of the lid sealing the IC package. The antenna may be placed in the floor or on a surface of the IC lid by forming depressions in the floor or lid surface and depositing conductive material in the depressions. The conductive material deposition may be by sputtering, evaporation, or other known physical or chemical deposition method. Antennas formed in the upper surface of an IC lid may be coupled to a pin of the IC package so that the antenna may be electrically coupled to a transceiver component on the IC within the package. Antennas formed in the lower surface of an IC lid or the floor of the IC package may be coupled by a conductive pin to a component pad of the IC within the package. To reduce electromagnetic noise that may be induced by the radio frequency signals emitted or received by an antenna, a grounding plane may be provided as part of the IC package. The grounding plane may be coupled to an electrical ground reference point through an IC package pin or the IC within the package.
摘要翻译：集成电路封装包括用于容纳集成电路（IC）的空腔和设置为基本上位于空腔外部的封装的一部分的天线。天线可以位于IC封装的位于IC腔外部区域的地板上。或者，天线可以位于盖的上表面或下表面上，密封IC封装。天线可以通过在地板或盖子表面中形成凹陷并在凹陷中沉积导电材料而放置在IC盖的地板或表面上。导电材料沉积可以通过溅射，蒸发或其它已知的物理或化学沉积方法。形成在IC盖的上表面中的天线可以耦合到IC封装的引脚，使得天线可以电耦合到封装内的IC上的收发器部件。形成在IC盖的下表面或IC封装的底板中的天线可以通过导电引脚耦合到封装内的IC的元件垫。为了减少由天线发射或接收的射频信号可能引起的电磁噪声，可以提供接地平面作为IC封装的一部分。接地平面可以通过封装中的IC封装引脚或IC耦合到电接地参考点。

5. 发明授权

US06837967B1 Method and apparatus for cleaning deposited films from the edge of a wafer 有权
标题翻译：从晶片边缘清除沉积膜的方法和装置
公开(公告)号：US06837967B1
公开(公告)日：2005-01-04
申请号：US10290437
申请日：2002-11-06
申请人： Michael J. Berman , Steven E. Reder , Rennie G. Barber
发明人： Michael J. Berman , Steven E. Reder , Rennie G. Barber
IPC分类号： H01J37/32 , H01L21/00 , H05H1/00
CPC分类号： H01L21/67069 , H01J37/3244 , H01J37/32623 , H01J37/32633 , H01L21/67028
摘要： A plasma edge cleaning apparatus is configured to remove film deposits from a wafer edge. A gas distribution manifold is annular shaped and positioned to provide plasma process gases near the edge of the wafer. A top insulator and a wafer support each include a magnetic coil to generate a magnetic field for shielding the selected portions of a wafer from the generated plasma. The top insulator is positioned above the wafer during edge processing so as to form a small gap between the top insulator and the wafer to prevent plasma from etching active die areas of the wafer.
摘要翻译：等离子体边缘清洁装置构造成从晶片边缘去除膜沉积物。气体分配歧管是环形的并且定位成在晶片的边缘附近提供等离子体处理气体。顶部绝缘体和晶片支架各自包括磁性线圈，以产生磁场，用于屏蔽所产生的等离子体的晶片的选定部分。顶部绝缘体在边缘处理期间位于晶片上方，以在顶部绝缘体和晶片之间形成小的间隙，以防止等离子体蚀刻晶片的有效裸片区域。

6. 发明授权

US07098996B1 Optical error minimization in a semiconductor manufacturing apparatus 有权
标题翻译：半导体制造装置中的光学误差最小化
公开(公告)号：US07098996B1
公开(公告)日：2006-08-29
申请号：US11075195
申请日：2005-03-07
申请人： Michael J. Berman , George E. Bailey
发明人： Michael J. Berman , George E. Bailey
IPC分类号： G03B27/54 , G03B27/62 , G03B27/68
CPC分类号： G03F1/64 , G03F1/62 , G03F7/70308 , G03F7/70425 , G03F7/70783 , G03F7/70983
摘要： Provided are systems and methods for overcoming optical errors occurring from reticle and other hardware usage in a semiconductor fabrication apparatus. The systems and methods minimize optical errors, such as those resulting from gravitational sag on a reticle or mask, for a pattern being projected onto a wafer. The reduced errors allow larger reticles and masks to be used—while maintaining optical accuracy; and also improve optical budget management.
摘要翻译：提供了用于克服半导体制造装置中的掩模版和其他硬件使用发生的光学误差的系统和方法。系统和方法将光学误差最小化，例如由于在掩模版或掩模上引起的重力下垂引起的误差，用于将图案投影到晶片上。减少的误差允许使用更大的掩模和掩模 - 同时保持光学精度; 并改善光预算管理。

7. 发明授权

US07023530B1 Dual source lithography for direct write application 失效
标题翻译：双源光刻直接写入应用
公开(公告)号：US07023530B1
公开(公告)日：2006-04-04
申请号：US11075239
申请日：2005-03-07
申请人： Michael J. Berman , George E. Bailey
发明人： Michael J. Berman , George E. Bailey
IPC分类号： G03B27/32 , G03B27/42 , G03B27/44
CPC分类号： B82Y10/00 , B82Y40/00 , G03F7/70383 , G03F7/7045 , H01J37/3174 , H01J2237/31757
摘要： A dual exposure source lithography system forms a first and a second portion of a pattern on a wafer. An optical lithography module forms the first portion of the pattern. A non-optical lithography module forms the second portion of the pattern using a non-optical lithography exposure source. The non-optical exposure source is an electron beam lithography source, an EUV source, an x-ray source, or another next generation lithography system exposure source. A mask design file is decomposed into separate design files reflecting critical and non-critical components of the pattern to be formed on the wafer.
摘要翻译：双曝光源光刻系统在晶片上形成图案的第一部分和第二部分。光学光刻模块形成图案的第一部分。非光学光刻模块使用非光学光刻曝光源形成图案的第二部分。非光学曝光源是电子束光刻源，EUV源，x射线源或另一下一代光刻系统曝光源。掩模设计文件被分解成反映要在晶片上形成的图案的关键和非关键部件的单独的设计文件。

8. 发明授权

US06894762B1 Dual source lithography for direct write application 失效
标题翻译：双源光刻直接写入应用
公开(公告)号：US06894762B1
公开(公告)日：2005-05-17
申请号：US10246286
申请日：2002-09-17
申请人： Michael J. Berman , George E. Bailey
发明人： Michael J. Berman , George E. Bailey
IPC分类号： G03B27/32 , G03B27/44 , G03B27/54 , G03F7/20 , H01J37/317
CPC分类号： B82Y10/00 , B82Y40/00 , G03F7/70383 , G03F7/7045 , H01J37/3174 , H01J2237/31757
摘要： A dual exposure source lithography system forms a first and a second portion of a pattern on a wafer. An optical lithography module forms the first portion of the pattern. A non-optical lithography module forms the second portion of the pattern using a non-optical lithography exposure source. The non-optical exposure source is an electron beam lithography source, an EUV source, an x-ray source, or another next generation lithography system exposure source. A mask design file is decomposed into separate design files reflecting critical and non-critical components of the pattern to be formed on the wafer.
摘要翻译：双曝光源光刻系统在晶片上形成图案的第一部分和第二部分。光学光刻模块形成图案的第一部分。非光学光刻模块使用非光学光刻曝光源形成图案的第二部分。非光学曝光源是电子束光刻源，EUV源，x射线源或另一下一代光刻系统曝光源。掩模设计文件被分解成反映要在晶片上形成的图案的关键和非关键部件的单独的设计文件。

9. 发明授权

US07298458B2 Optical error minimization in a semiconductor manufacturing apparatus 有权
标题翻译：半导体制造装置中的光学误差最小化
公开(公告)号：US07298458B2
公开(公告)日：2007-11-20
申请号：US11473627
申请日：2006-06-22
申请人： Michael J. Berman , George E. Bailey
发明人： Michael J. Berman , George E. Bailey
IPC分类号： G03B27/62 , G03B27/68
CPC分类号： G03F1/64 , G03F1/62 , G03F7/70308 , G03F7/70425 , G03F7/70783 , G03F7/70983
摘要： Provided are systems and methods for overcoming optical errors occurring from reticle and other hardware usage in a semiconductor fabrication apparatus. The systems and methods minimize optical errors, such as those resulting from gravitational sag on a reticle or mask, for a pattern being projected onto a wafer. The reduced errors allow larger reticles and masks to be used—while maintaining optical accuracy; and also improve optical budget management.
摘要翻译：提供了用于克服半导体制造装置中的掩模版和其他硬件使用发生的光学误差的系统和方法。系统和方法将光学误差最小化，例如由于在掩模版或掩模上引起的重力下垂引起的误差，用于将图案投影到晶片上。减少的误差允许使用更大的掩模和掩模 - 同时保持光学精度; 并改善光预算管理。

10. 发明授权

US06885436B1 Optical error minimization in a semiconductor manufacturing apparatus 失效
标题翻译：半导体制造装置中的光学误差最小化
公开(公告)号：US06885436B1
公开(公告)日：2005-04-26
申请号：US10243562
申请日：2002-09-13
申请人： Michael J. Berman , George E. Bailey
发明人： Michael J. Berman , George E. Bailey
IPC分类号： G03F1/14 , G03F7/20 , G03B27/54 , G03B27/62 , G03B27/68
CPC分类号： G03F1/64 , G03F1/62 , G03F7/70308 , G03F7/70425 , G03F7/70783 , G03F7/70983
摘要： Provided are systems and methods for overcoming optical errors occurring from reticle and other hardware usage in a semiconductor fabrication apparatus. The systems and methods minimize optical errors, such as those resulting from gravitational sag on a reticle or mask, for a pattern being projected onto a wafer. The reduced errors allow larger reticles and masks to be used—while maintaining optical accuracy; and also improve optical budget management.
摘要翻译：提供了用于克服半导体制造装置中的掩模版和其他硬件使用发生的光学误差的系统和方法。系统和方法将光学误差最小化，例如由于在掩模版或掩模上引起的重力下垂引起的误差，用于将图案投影到晶片上。减少的误差允许使用更大的掩模和掩模 - 同时保持光学精度; 并改善光预算管理。

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