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1. 发明申请

US20050160097A1 SIMD-RISC microprocessor architecture 失效
标题翻译： SIMD-RISC微处理器架构
公开(公告)号：US20050160097A1
公开(公告)日：2005-07-21
申请号：US11065707
申请日：2005-02-24
申请人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
发明人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
IPC分类号： G06F15/16 , G06F9/44 , G06F9/50 , G06F15/177 , G06F15/80 , H04L29/06 , H04L29/08 , G06F17/30
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

2. 发明申请

US20070186077A1 System and Method for Executing Instructions Utilizing a Preferred Slot Alignment Mechanism 审中-公开
标题翻译：使用优选插槽对准机制执行指令的系统和方法
公开(公告)号：US20070186077A1
公开(公告)日：2007-08-09
申请号：US11461554
申请日：2006-08-01
申请人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
发明人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
IPC分类号： G06F15/00
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into four “slots,” each including four bytes, and locates scalar data in “preferred slots” to ensure proper positioning. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). As a result, the processor architecture eliminates the requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units.
摘要翻译：提出了一种利用优选槽对准机构执行指令的系统和方法。处理器架构使用向量寄存器文件，共享数据路径和指令执行逻辑来处理单指令多数据（SIMD）指令和标量指令。处理器架构将向量分成四个“时隙”，每个“插槽”包括四个字节，并将标量数据定位在“首选插槽”中，以确保正确定位。使用首选插槽机制的指令包括1）移动和旋转指定移位量的整个四字的操作指令，2）需要地址的存储器加载和存储指令，以及3）使用首选插槽进行分支的分支指令条件（条件分支）和分支地址（寄存器 - 间接分支）。因此，处理器架构消除了单独的问题槽，独立的管道和单独标量单元的控制复杂性的要求。

3. 发明申请

US20060190614A1 Non-homogeneous multi-processor system with shared memory 失效
公开(公告)号：US20060190614A1
公开(公告)日：2006-08-24
申请号：US11065537
申请日：2005-02-24
申请人： Erik Altman , Peter Capek , Michael Gschwind , Charles Johns , Harm Hofstee , Martin Hopkins , James Kahle , Sumedh Sathaye , John-David Wellman
发明人： Erik Altman , Peter Capek , Michael Gschwind , Charles Johns , Harm Hofstee , Martin Hopkins , James Kahle , Sumedh Sathaye , John-David Wellman
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

4. 发明申请

US20060155955A1 SIMD-RISC processor module 审中-公开
标题翻译： SIMD-RISC处理器模块
公开(公告)号：US20060155955A1
公开(公告)日：2006-07-13
申请号：US11032194
申请日：2005-01-10
申请人： Michael Gschwind , Charles Johns , Harm Hofstee , James Kahle
发明人： Michael Gschwind , Charles Johns , Harm Hofstee , James Kahle
IPC分类号： G06F15/00
CPC分类号： G06F15/8007 , G06F13/1663
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

5. 发明申请

US20070168538A1 Computer architecture and software cells for broadband networks 有权
公开(公告)号：US20070168538A1
公开(公告)日：2007-07-19
申请号：US11716845
申请日：2007-03-12
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Hofstee , Martin Hopkins , Charles Johns , James Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Hofstee , Martin Hopkins , Charles Johns , James Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

6. 发明申请

US20060031836A1 Hierarchical management for multiprocessor system with real-time attributes 失效
标题翻译：具有实时属性的多处理器系统的分层管理
公开(公告)号：US20060031836A1
公开(公告)日：2006-02-09
申请号：US10912481
申请日：2004-08-05
申请人： Jeffrey Brown , Michael Day , Harm Hofstee , Charles Johns , James Kahle , Michael Wang
发明人： Jeffrey Brown , Michael Day , Harm Hofstee , Charles Johns , James Kahle , Michael Wang
IPC分类号： G06F9/46
CPC分类号： G06F1/3203
摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.
摘要翻译：本发明提供用于控制元件的功耗。第一个功率控制命令由该元件的软件发出。确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。该软件是实时软件，软件还设置了最低限度可接受的活动控制状态。通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

7. 发明申请

US20050268048A1 System and method for using a plurality of heterogeneous processors in a common computer system 审中-公开
标题翻译：在普通计算机系统中使用多个异构处理器的系统和方法
公开(公告)号：US20050268048A1
公开(公告)日：2005-12-01
申请号：US11171757
申请日：2005-06-30
申请人： Harm Hofstee , Charles Johns , James Kahle
发明人： Harm Hofstee , Charles Johns , James Kahle
IPC分类号： G06F15/16 , G06F9/44 , G06F9/50 , G06F15/177 , G06F15/80 , H04L29/06 , H04L29/08 , G06F13/00
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A system for using a plurality of heterogeneous processors in a common computer system is presented. Each processor type in the heterogeneous group handles a particular instruction set. The processors share a common memory using a common bus. In one embodiment, one of the processor types accesses the memory using DMA instructions. In another embodiment, a cache for each type of processor is stored in the common memory pool. In one embodiment, one or more PowerPC processors shares a memory with one or more Synergistic Processing Complex (SPC). A common table is used to track and maintain memory for the various processors.
摘要翻译：提出了一种在普通计算机系统中使用多个异构处理器的系统。异构组中的每个处理器类型处理特定的指令集。处理器使用公共总线共享共享内存。在一个实施例中，处理器类型之一使用DMA指令访问存储器。在另一个实施例中，用于每种类型的处理器的高速缓存存储在公共存储器池中。在一个实施例中，一个或多个PowerPC处理器与一个或多个协同处理复合体（SPC）共享存储器。通用表用于跟踪和维护各种处理器的内存。

8. 发明申请

US20050080998A1 Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
标题翻译：异构处理器系统的相干存储器结构的方法和装置
公开(公告)号：US20050080998A1
公开(公告)日：2005-04-14
申请号：US10682386
申请日：2003-10-09
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong
IPC分类号： G06F12/08
CPC分类号： G06F12/0835
摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.
摘要翻译：公开了与非均匀处理单元结合操作的一致的缓存系统。一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

9. 发明申请

US20050138325A1 Multi-chip module with third dimension interconnect 审中-公开
标题翻译：具有三维互连的多芯片模块
公开(公告)号：US20050138325A1
公开(公告)日：2005-06-23
申请号：US11050038
申请日：2005-02-03
申请人： Harm Hofstee , Charles Johns , James Kahle
发明人： Harm Hofstee , Charles Johns , James Kahle
IPC分类号： G06F15/16 , G06F9/44 , G06F9/50 , G06F15/177 , G06F15/80 , H04L29/06 , H04L29/08 , G06F15/00 , G06F15/173
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

10. 发明申请

US20050055505A1 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US20050055505A1
公开(公告)日：2005-03-10
申请号：US10655365
申请日：2003-09-04
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

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