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1. 发明申请

US20070168538A1 Computer architecture and software cells for broadband networks 有权
公开(公告)号：US20070168538A1
公开(公告)日：2007-07-19
申请号：US11716845
申请日：2007-03-12
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Hofstee , Martin Hopkins , Charles Johns , James Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Hofstee , Martin Hopkins , Charles Johns , James Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

2. 发明申请

US20060190614A1 Non-homogeneous multi-processor system with shared memory 失效
公开(公告)号：US20060190614A1
公开(公告)日：2006-08-24
申请号：US11065537
申请日：2005-02-24
申请人： Erik Altman , Peter Capek , Michael Gschwind , Charles Johns , Harm Hofstee , Martin Hopkins , James Kahle , Sumedh Sathaye , John-David Wellman
发明人： Erik Altman , Peter Capek , Michael Gschwind , Charles Johns , Harm Hofstee , Martin Hopkins , James Kahle , Sumedh Sathaye , John-David Wellman
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

3. 发明申请

US20050160097A1 SIMD-RISC microprocessor architecture 失效
标题翻译： SIMD-RISC微处理器架构
公开(公告)号：US20050160097A1
公开(公告)日：2005-07-21
申请号：US11065707
申请日：2005-02-24
申请人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
发明人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
IPC分类号： G06F15/16 , G06F9/44 , G06F9/50 , G06F15/177 , G06F15/80 , H04L29/06 , H04L29/08 , G06F17/30
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

4. 发明申请

US20070186077A1 System and Method for Executing Instructions Utilizing a Preferred Slot Alignment Mechanism 审中-公开
标题翻译：使用优选插槽对准机制执行指令的系统和方法
公开(公告)号：US20070186077A1
公开(公告)日：2007-08-09
申请号：US11461554
申请日：2006-08-01
申请人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
发明人： Michael Gschwind , Harm Hofstee , Martin Hopkins , James Kahle
IPC分类号： G06F15/00
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into four “slots,” each including four bytes, and locates scalar data in “preferred slots” to ensure proper positioning. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). As a result, the processor architecture eliminates the requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units.
摘要翻译：提出了一种利用优选槽对准机构执行指令的系统和方法。处理器架构使用向量寄存器文件，共享数据路径和指令执行逻辑来处理单指令多数据（SIMD）指令和标量指令。处理器架构将向量分成四个“时隙”，每个“插槽”包括四个字节，并将标量数据定位在“首选插槽”中，以确保正确定位。使用首选插槽机制的指令包括1）移动和旋转指定移位量的整个四字的操作指令，2）需要地址的存储器加载和存储指令，以及3）使用首选插槽进行分支的分支指令条件（条件分支）和分支地址（寄存器 - 间接分支）。因此，处理器架构消除了单独的问题槽，独立的管道和单独标量单元的控制复杂性的要求。

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