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1. 发明申请

US20080148104A1 Detecting an Agent Generating a Parity Error on a PCI-Compatible Bus 审中-公开
标题翻译：检测在PCI兼容总线上产生奇偶校验错误的代理
公开(公告)号：US20080148104A1
公开(公告)日：2008-06-19
申请号：US11469635
申请日：2006-09-01
申请人： Michael G. Brinkman , Timothy J. Schlude , Gregory D. Sellman
发明人： Michael G. Brinkman , Timothy J. Schlude , Gregory D. Sellman
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/0772 , G06F11/0787
摘要： Methods, apparatus, and products are disclosed for detecting an agent generating a parity error on a PCI-compatible bus that include detecting, by an administrative agent on the bus, a parity error that occurred during a transaction on a PCI-compatible bus that connects a plurality of agents for data communications, retrieving, by the administrative agent, a value for a grant signal associated with each agent on the bus for the transaction, retrieving, by the administrative agent, values for an address signal and a command signal for the transaction, and identifying, by the administrative agent, the agent generating the parity error in dependence upon the values for the grant signals, the address signal, and the command signal.
摘要翻译：公开了用于检测在PCI兼容总线上产生奇偶校验错误的代理的方法，装置和产品，其包括由总线上的管理代理检测在连接的PCI兼容总线上的事务期间发生的奇偶校验错误用于数据通信的多个代理，由管理代理检索与用于交易的总线上的每个代理相关联的授权信号的值，由管理代理检索用于地址信号的值和用于交易，以及由管理代理人根据授权信号，地址信号和命令信号的值产生奇偶校验错误的代理。

2. 发明授权

US09917033B2 Multicomponent heat sink with movable fin support portion 有权
公开(公告)号：US09917033B2
公开(公告)日：2018-03-13
申请号：US13533376
申请日：2012-06-26
申请人： William M. Megarity, Jr. , Luke D. Remis , Gregory D. Sellman
发明人： William M. Megarity, Jr. , Luke D. Remis , Gregory D. Sellman
IPC分类号： H01L23/40
CPC分类号： H01L23/4006 , H01L2023/4081 , H01L2924/0002 , Y10T29/49826 , H01L2924/00
摘要： A heat sink comprises a base and a fin support larger in area than the base and supporting fins that may be positioned in a plurality of orientations relative to the base. The base is adapted for being connected to a heat-generating electronic component on a circuit board, and the heat sink dissipates heat generated by the heat-generating electronic device and conducted through the base and the fin support to the fins supported thereon. The heat sink dissipates heat from the heat-generating electronic device in a first operable position and in a second operable position. The heat sink may be moved from the first to the second operable position to facilitate access to electrical contacts proximal the heat-generating electronic component.

3. 发明授权

US08900008B2 Universal press-fit connection for printed circuit boards 有权
标题翻译：印刷电路板的通用压配连接
公开(公告)号：US08900008B2
公开(公告)日：2014-12-02
申请号：US13481176
申请日：2012-05-25
申请人： James A. Day, Jr. , Zachary B. Durham , Luke D. Remis , Tony C. Sass , Gregory D. Sellman
发明人： James A. Day, Jr. , Zachary B. Durham , Luke D. Remis , Tony C. Sass , Gregory D. Sellman
IPC分类号： H01R13/60
CPC分类号： H05K13/04 , H01R12/585 , H05K1/115 , H05K3/308 , H05K3/325 , H05K2201/09845 , H05K2201/1059 , H05K2201/10856 , H05K2201/10878
摘要： A universal press-fit connection allows a component having a connector pin to be connected to a compatible plated through hole of a circuit board regardless of circuit board thickness. The connector pin includes a proximate end adjacent the component, a distal end with a fork lock, and a compliant portion between the proximate and distal ends. A multi-width through hole includes a first portion partially extending through the circuit board and a second, wider portion extending beyond the first portion. The fork lock initially moves radially inward upon insertion into the first portion via flexing of the compliant portion, and re-expands when entering the second portion. The compliant portion engages the through hole and the fork lock secures the connector pin in the through hole.
摘要翻译：通用压配合连接允许具有连接器引脚的部件连接到电路板的兼容的电镀通孔，而与电路板厚度无关。连接器销包括邻近部件的近端，具有叉锁的远端以及近端和远端之间的柔顺部分。多宽度通孔包括部分延伸穿过电路板的第一部分和延伸超过第一部分的第二较宽部分。当通过柔性部分的弯曲插入到第一部分中时，叉锁首先向内径向移动，并且当进入第二部分时，叉锁重新膨胀。柔性部分接合通孔，叉锁将连接器销固定在通孔中。

4. 发明申请

US20140071647A1 INTEGRATED CIRCUIT RETENTION MECHANISM WITH RETRACTABLE COVER 有权
标题翻译：集成电路保留机制与可复封
公开(公告)号：US20140071647A1
公开(公告)日：2014-03-13
申请号：US13610923
申请日：2012-09-12
申请人： Jeremy S. Bridges , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Jeremy S. Bridges , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： H05K7/00
CPC分类号： H05K7/1429 , H01L23/40 , H01L23/4006 , H01L2023/4056 , H01L2023/4068 , H01L2023/4087 , H01L2924/0002 , H05K7/1007 , H01L2924/00
摘要： A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.
摘要翻译：计算机处理器保持装置包括负载框架，负载板和一对可缩回盖构件。负载框架可以固定到处理器安装位置周围的电路板。负载板枢转地联接到负载框架，并且可在打开状态之间枢转，以在处理器安装位置处接收处理器并且与接收到的处理器的外围封闭。当负载板关闭时，负载板具有对处理器安装位置开放的窗口。可缩回的盖构件跨越窗户，并且可沿轨道彼此交替移动以覆盖处理器安装位置并远离彼此以暴露处理器安装位置。

5. 发明申请

US20140013151A1 I2C MULTIPLEXER SWITCHING AS A FUNCTION OF CLOCK FREQUENCY 有权
标题翻译： I2C多路复用器切换作为时钟频率的功能
公开(公告)号：US20140013151A1
公开(公告)日：2014-01-09
申请号：US13541750
申请日：2012-07-04
申请人： Michael DeCesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
发明人： Michael DeCesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F1/04 , G06F13/36
CPC分类号： G06F13/4282
摘要： In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.
摘要翻译：根据本发明的一个实施例，可以提供用于I2C总线接口的I2C总线复用电路。 I2C总线复用电路可以通过I2C总线从I2C主器件检测启动命令，缓冲来自I2C主器件的数据，检测总线串行时钟（SCL）线的时钟频率，从而有助于I2C总线接口中的多路开关切换的I2C主器件，将I2C主器件的串行数据（SDA）线保持在时钟拉伸状态，并根据检测到的I2C主器件SCL的时钟频率选择一个端口。该方法还可以包括将所缓冲的数据发送到所选端口上的I2C从设备。该方法还可以包括从所选端口上的I2C从设备接收确认。

6. 发明授权

US07467311B2 Distributed system and method for managing power usage among server data processing systems 失效
标题翻译：用于管理服务器数据处理系统中的电力使用的分布式系统和方法
公开(公告)号：US07467311B2
公开(公告)日：2008-12-16
申请号：US11148579
申请日：2005-06-09
申请人： Sumanta K. Bahali , Warren D. Bailey , Jimmy G. Foster, Sr. , Gregory D. Sellman
发明人： Sumanta K. Bahali , Warren D. Bailey , Jimmy G. Foster, Sr. , Gregory D. Sellman
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： A distributed method and system for managing power usage among server data processing systems are disclosed. According to one embodiment, a server data processing system of a plurality of server data processing systems is provided, where the server data processing system comprises a power management communication port to communicatively couple the server data processing system to all other server data processing systems of the plurality of server data processing systems and a system management processor coupled to the power management communication port. In the described embodiment, the system management processor comprises communication logic configured to monitor power usage of all the other server data processing systems of the plurality, and power management logic configured to perform a power management operation on the server data processing system based upon the monitored power usage.
摘要翻译：公开了一种用于管理服务器数据处理系统中的电力使用的分布式方法和系统。根据一个实施例，提供了多个服务器数据处理系统的服务器数据处理系统，其中服务器数据处理系统包括电源管理通信端口，用于将服务器数据处理系统通信地耦合到所有其他服务器数据处理系统多个服务器数据处理系统和耦合到电源管理通信端口的系统管理处理器。在所描述的实施例中，系统管理处理器包括被配置为监视所有其他服务器数据处理系统的功率使用的通信逻辑，以及被配置为基于所监视的服务器数据处理系统对服务器数据处理系统执行电力管理操作的电源管理逻辑电力使用

7. 发明授权

US09411770B2 Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select 有权
标题翻译：使用单个芯片选择来控制多个串行外设接口（“SPI”）外设
公开(公告)号：US09411770B2
公开(公告)日：2016-08-09
申请号：US13545581
申请日：2012-07-10
申请人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
发明人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F3/00 , G06F13/12 , G06F13/42
CPC分类号： G06F13/4291
摘要： Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.
摘要翻译：计算系统中使用单个芯片选择来控制多个串行外设接口（“SPI”）外围设备，所述计算系统包括SPI主机，第一SPI外设和第二SPI外设，其中第一SPI外设可操作地耦合到第二个SPI外设，包括：由第一个SPI外设接收来自SPI主机的信号; 由第一SPI外设确定第一个SPI外设是主SPI外设还是备用SPI外设; 响应于确定第一SPI外设是备用SPI外设，由第一SPI外设向第二SPI外设发送该信号; 并且响应于确定第一SPI外设是主SPI外设：由第一SPI外设处理包含在该信号中的指令; 以及由所述第一SPI外设向所述第二SPI外设发送响应信号。

8. 发明授权

US08984196B2 Accessing peripheral devices 有权
标题翻译：访问外围设备
公开(公告)号：US08984196B2
公开(公告)日：2015-03-17
申请号：US13445235
申请日：2012-04-12
申请人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
发明人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F13/00
CPC分类号： G06F13/4291
摘要： A hardware system comprises a master device and a slave device that are coupled by a signal line. A frequency generator in the master device places a selected frequency signal on the signal line. A frequency detector/comparator in the slave device, which is coupled to the signal line, determines whether the selected frequency signal on the signal line matches a predetermined frequency for the slave device. If the selected frequency signal matches the predetermined frequency, then a chip select node on the slave device is enabled, in order to permit a data exchange session between the master device and the slave device.
摘要翻译：硬件系统包括通过信号线耦合的主设备和从设备。主设备中的频率发生器将选定的频率信号放置在信号线上。耦合到信号线的从设备中的频率检测器/比较器确定信号线上选定的频率信号是否与从设备的预定频率相匹配。如果所选择的频率信号与预定频率匹配，则从设备上的片选选择节点被使能，以便允许主设备和从设备之间的数据交换会话。

9. 发明授权

US08831772B2 Lift apparatus for stable placement of components into a rack 有权
标题翻译：用于将部件稳定放置到机架中的提升装置
公开(公告)号：US08831772B2
公开(公告)日：2014-09-09
申请号：US13557357
申请日：2012-07-25
申请人： Jeremy S. Bridges , Michael DeCesaris , Luke D. Remis , Gregory D. Sellman
发明人： Jeremy S. Bridges , Michael DeCesaris , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F7/00 , G06F17/50
CPC分类号： G11B15/68
摘要： A method uses scales onboard a lift apparatus to weigh an uninstalled component that is positioned on the lift apparatus for installation into a rack. Data is accessed that identifies the weight and rack location of components currently installed in the rack, and one or more available rack locations are identified where the component may be installed without violating one or more predetermined rack stability rules. The method then uses the lift apparatus to raise the component into a selected one of the one or more available rack locations. The components are preferably information technology components, such as servers, network switches and power distribution units.
摘要翻译：一种方法使用升降机装置上的刻度来称重位于升降机装置上的用于安装到机架中的卸载部件。访问数据，其识别当前安装在机架中的部件的重量和机架位置，并且识别可以安装部件的一个或多个可用的机架位置，而不违反一个或多个预定的机架稳定性规则。该方法然后使用提升装置将部件升高成一个或多个可用的机架位置中的选定的一个。这些组件优选地是诸如服务器，网络交换机和配电单元之类的信息技术组件。

10. 发明申请

US20140019644A1 Controlling A Plurality Of Serial Peripheral Interface ('SPI') Peripherals Using A Single Chip Select 有权
标题翻译：使用单片选择控制多个串行外设接口（“SPI”）外设
公开(公告)号：US20140019644A1
公开(公告)日：2014-01-16
申请号：US13545581
申请日：2012-07-10
申请人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
发明人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F3/00
CPC分类号： G06F13/4291
摘要： Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.
摘要翻译：计算系统中使用单个芯片选择来控制多个串行外设接口（“SPI”）外围设备，所述计算系统包括SPI主机，第一SPI外设和第二SPI外设，其中第一SPI外设可操作地耦合到第二个SPI外设，包括：由第一个SPI外设接收来自SPI主机的信号; 由第一SPI外设确定第一个SPI外设是主SPI外设还是备用SPI外设; 响应于确定第一SPI外设是备用SPI外设，由第一SPI外设向第二SPI外设发送该信号; 并且响应于确定第一SPI外设是主SPI外设：由第一SPI外设处理包含在该信号中的指令; 以及由所述第一SPI外设向所述第二SPI外设发送响应信号。

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