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1. 发明授权

US07035755B2 Circuit testing with ring-connected test instrument modules 失效
公开(公告)号：US07035755B2
公开(公告)日：2006-04-25
申请号：US10222191
申请日：2002-08-16
申请人： Michael F. Jones , Robert Whyte , Jamie S. Cullen , Naveed Zaman , Yann Gazounaud , Burnell G. West , William Fritzsche
发明人： Michael F. Jones , Robert Whyte , Jamie S. Cullen , Naveed Zaman , Yann Gazounaud , Burnell G. West , William Fritzsche
IPC分类号： G06F11/273
CPC分类号： G01R31/31907 , G01R31/31922
摘要： Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

2. 发明授权

US5748124A Analog channel for mixed-signal-VLSI tester 失效
公开(公告)号：US5748124A
公开(公告)日：1998-05-05
申请号：US762395
申请日：1996-12-09
申请人： Daniel Rosenthal , Kannan Konath , Robert Whyte , Eric Norton , Stuart Robert Pearce
发明人： Daniel Rosenthal , Kannan Konath , Robert Whyte , Eric Norton , Stuart Robert Pearce
IPC分类号： G01R31/316 , G01R31/3167 , G01R31/317 , G06F3/05 , G06F11/22 , H03M1/10
CPC分类号： G01R31/3167 , G01R31/31716
摘要： Mixed-signal tester architecture and methods are provided which minimize transfer of data, offer parallel data post-processing within the analog channels, and allow flexible synchronization. Multiple analog channels each have a source digital signal processor (DSP), a digital source sequencer, digital source instrumentation, analog source instrumentation, analog measure instrumentation, digital measure instrumentation, a digital pin multiplexer, a digital measure sequencer, DSP-addressable multi-bank capture memory, a capture digital signal processor, and an inter-DSP feedback path for communication between the source DSP and the capture DSP. Each analog channel can be arranged in a feedback loop through either its analog and/or digital instrumentation using the inter-DSP feedback path. DUT response is processed in the channel, the result is used to define parameters for a subsequent test cycle, and a signal corresponding to these parameters is generated and applied to the DUT. This loop-back of the result of a test cycle within the analog channel to define the next test cycle speeds up the test process. The source DSP can synthesize signals in real time and apply these to the DUT through analog or digital source instrumentation, and can synthesize source sequencer memory addresses (pointers to waveform-data stored in memory which represent waveforms or waveform segments) in real time and apply these signals to the DUT through analog or digital source instrumentation. DUT response is written to capture-memory in the channel which is directly addressable by the capture DSP, avoiding transfer of data before processing and further speeding the test process. Multi-bank capture memory controlled by the capture DSP allows data representing DUT response to be written into one bank while previously-written data in another bank is processed. This interleaving of data capture and data processing allows simultaneous capture and processing, further speeding the test process.

3. 发明申请

US20050009378A1 Hard disk drive (HDD) electrical over voltage stress (EOS) systems and methods 有权
标题翻译：硬盘驱动器（HDD）电气过压应力（EOS）系统和方法
公开(公告)号：US20050009378A1
公开(公告)日：2005-01-13
申请号：US10913604
申请日：2004-08-05
申请人： James Chloupek , Robert Whyte
发明人： James Chloupek , Robert Whyte
IPC分类号： H02H9/04 , H02H11/00 , H02B1/056
CPC分类号： H02H11/007 , H02H9/04
摘要： The present invention relates to a hard disk drive system having overvoltage protection circuits for various types of overvoltage conditions. For example, the system comprises one or more hard disk drive integrated circuit chips residing on a board and a hard disk drive power plug receptacle residing on the board having two different value power supply ports associated therewith. The receptacle is operable to receive a power plug therein, wherein when the power plug is inserted therein in a proper orientation the two different value voltages are properly supplied to the one or more hard disk drive integrated circuit chips, and wherein when the power plug is inserted therein in an improper orientation the two different value voltages are switched with respect to their intended values. The system comprises a reverse power plug orientation protection circuit coupled between the hard disk drive power plug receptacle and at least one of the one or more hard disk drive integrated circuit chips. The protection circuit is operable to detect an improper orientation of the power plug when inserted into the hard disk drive power plug receptacle and reduce a larger of the two different voltage values, thereby preventing an electrical over voltage stress of the at least one hard disk drive integrated circuit chip.
摘要翻译：本发明涉及具有用于各种过电压条件的过电压保护电路的硬盘驱动系统。例如，系统包括位于板上的一个或多个硬盘驱动器集成电路芯片和驻留在板上的硬盘驱动器电源插头插座，其具有与其相关联的两个不同值的电源端口。所述插座可操作以在其中接收电源插头，其中当所述电源插头以正确方向插入其中时，将两个不同的电压值适当地提供给所述一个或多个硬盘驱动器集成电路芯片，并且其中当所述电源插头以不适当的方向插入其中，两个不同的值电压相对于其预期值被切换。该系统包括耦合在硬盘驱动器电源插头插座和一个或多个硬盘驱动器集成电路芯片中的至少一个之间的反向电源插头取向保护电路。保护电路可操作以检测插入到硬盘驱动器电源插座中时电源插头的不正确方向，并减小两个不同电压值中较大的一个，从而防止至少一个硬盘驱动器的过电压应力集成电路芯片。

4. 外观设计

USD645762S1 Flexible beverage container 有权
标题翻译：柔性饮料容器
公开(公告)号：USD645762S1
公开(公告)日：2011-09-27
申请号：US29391566
申请日：2011-05-10
申请人： Sehee Hong , Robert Whyte
设计人： Sehee Hong , Robert Whyte

5. 发明授权

US5646521A Analog channel for mixed-signal-VLSI tester 失效
公开(公告)号：US5646521A
公开(公告)日：1997-07-08
申请号：US510397
申请日：1995-08-01
申请人： Daniel Rosenthal , Kannan Konath , Robert Whyte , Eric Norton , Stuart Robert Pearce
发明人： Daniel Rosenthal , Kannan Konath , Robert Whyte , Eric Norton , Stuart Robert Pearce
IPC分类号： G01R31/316 , G01R31/3167 , G01R31/317 , G06F3/05 , G06F11/22 , G01R31/28
CPC分类号： G01R31/3167 , G01R31/31716
摘要： Mixed-signal tester architecture and methods are provided which minimize transfer of data, offer parallel data post-processing within the analog channels, and allow flexible synchronization. Multiple analog channels each have a source digital signal processor (DSP), a digital source sequencer, digital source instrumentation, analog source instrumentation, analog measure instrumentation, digital measure instrumentation, a digital pin multiplexer, a digital measure sequencer, DSP-addressable multi-bank capture memory, a capture digital signal processor, and an inter-DSP feedback path for communication between the source DSP and the capture DSP. Each analog channel can be arranged in a feedback loop through either its analog and/or digital instrumentation using the inter-DSP feedback path. DUT response is processed in the channel, the result is used to define parameters for a subsequent test cycle, and a signal corresponding to these parameters is generated and applied to the DUT. This loop-back of the result of a test cycle within the analog channel to define the next test cycle speeds up the test process. The source DSP can synthesize signals in real time and apply these to the DUT through analog or digital source instrumentation, and can synthesize source sequencer memory addresses (pointers to waveform-data stored in memory which represent waveforms or waveform segments) in real time and apply these signals to the DUT through analog or digital source instrumentation. DUT response is written to capture-memory in the channel which is directly addressable by the capture DSP, avoiding transfer of data before processing and further speeding the test process. Multi-bank capture memory controlled by the capture DSP allows data representing DUT response to be written into one bank while previously-written data in another bank is processed. This interleaving of data capture and data processing allows simultaneous capture and processing, further speeding the test process.

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