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1. 发明授权

US08832343B2 Double density I2C system 有权
标题翻译：双密度I2C系统
公开(公告)号：US08832343B2
公开(公告)日：2014-09-09
申请号：US13550715
申请日：2012-07-17
申请人： Michael Decesaris , Jeffrey M. Franke , Luke D. Remis , John K. Whetzel
发明人： Michael Decesaris , Jeffrey M. Franke , Luke D. Remis , John K. Whetzel
IPC分类号： G06F13/00 , G06F13/38 , G06F13/42
CPC分类号： G06F13/4022 , G06F2213/0016
摘要： An I2C system comprises an inter-integrated circuit (I2C) master device coupled to an I2C multiplexer via a master I2C bus. A plurality of slave I2C busses emanating from the I2C multiplexer couple the I2C multiplexer to a plurality of I2C slave devices. Each of the slave I2C busses comprises a serial data (SDA) line and serial clock (SCL) line. Each of the slave I2C busses, which is coupled to two I2C slave devices, has a first channel and a second channel. The first channel puts bidirectional serial data on the SDA line and clock signals on the SCL line, and the second channel puts bidirectional serial data on the SCL line and clock signals on the SDA line. A channel selector, associated with the I2C multiplexer, selectively couples the I2C master device to one of the two I2C slave devices via the first channel or the second channel.
摘要翻译： I2C系统包括通过主I2C总线耦合到I2C多路复用器的集成电路（I2C）主器件。从I2C多路复用器发出的多个从属I2C总线将I2C多路复用器耦合到多个I2C从器件。每个从I2C总线包括串行数据（SDA）线和串行时钟（SCL）线。耦合到两个I2C从器件的每个从I2C总线具有第一通道和第二通道。第一个通道将SDA线上的双向串行数据和SCL线上的时钟信号放在一起，第二个通道将SCL线上的双向串行数据和SDA线上的时钟信号。与I2C多路复用器相关的通道选择器通过第一通道或第二通道将I2C主器件选择性地耦合到两个I2C从器件中的一个。

2. 发明授权

US09098645B2 Increasing data transmission rate in an inter-integrated circuit (‘I2C’) system 有权
标题翻译：在集成电路（“I2C”）系统中增加数据传输速率
公开(公告)号：US09098645B2
公开(公告)日：2015-08-04
申请号：US13530473
申请日：2012-06-22
申请人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman
发明人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F1/04 , G06F1/12 , G06F5/06 , G06F13/42
CPC分类号： G06F13/4291 , G06F2213/0016
摘要： Increasing data transmission rate in an I2C system that includes an I2C source device and an destination device, the source device coupled to the destination device through an SDL and SCL, including: receiving in parallel, by the destination device, an SDL data signal and an SCL data signal, the SCL data signal encoded with bits; and, for each bit of the SCL data signal: detecting rise time of the bit and determining, in dependence upon the detected rise time, whether the bit represents a first binary value or a second binary value including: determining that the bit represents a first binary value when the detected rise time is less than a predefined threshold; and determining that the bit represents a second binary value when the detected rise time is not less than the predefined threshold.
摘要翻译：包括I2C源设备和目标设备的I2C系统中的数据传输速率提高，源设备通过SDL和SCL耦合到目标设备，包括：由目标设备并行接收SDL数据信号和 SCL数据信号，SCL数据信号用位编码; 并且对于SCL数据信号的每一位：检测位的上升时间，并且根据检测到的上升时间确定该位是否表示第一二进制值或第二二进制值，包括：确定该位表示第一个当检测到的上升时间小于预定阈值时，二进制值; 以及当所检测的上升时间不小于所述预定阈值时，确定所述比特表示第二二进制值。

3. 发明授权

US08811587B2 Selectively filtering incoming communications events in a communications device 有权
标题翻译：选择性地过滤通信设备中的传入通信事件
公开(公告)号：US08811587B2
公开(公告)日：2014-08-19
申请号：US13444389
申请日：2012-04-11
申请人： Michael Decesaris , William M. Megarity , Luke D. Remis , Gregory D. Sellman
发明人： Michael Decesaris , William M. Megarity , Luke D. Remis , Gregory D. Sellman
IPC分类号： H04M3/42 , G06F15/173
CPC分类号： H04W4/16 , H04M3/436
摘要： Selectively filtering incoming communications events in a communications device, including: receiving, by a communications event filtering module, an incoming communications event; determining, by the communications event filtering module, whether the communications device is currently servicing a call; responsive to determining that the communications device is currently servicing a call, determining, by the communications event filtering module, whether the call is interruptible; and responsive to determining that the call is not interruptible, blocking, by the communications event filtering module, the incoming communications event from presentation by the communications device until the call has ended.
摘要翻译：在通信设备中选择性地过滤进入的通信事件，包括：由通信事件过滤模块接收进入的通信事件; 由所述通信事件过滤模块确定所述通信设备当前是否正在服务于呼叫; 响应于确定所述通信设备当前正在服务于呼叫，由所述通信事件过滤模块确定所述呼叫是否可中断; 并且响应于确定所述呼叫不可中断，所述通信事件过滤模块阻止所述通信设备的呼入通信事件，直到所述呼叫结束为止。

4. 发明授权

US08959380B2 Dynamically optimizing bus frequency of an inter-integrated circuit (‘I2C’) bus 有权
标题翻译：动态优化集成电路（“I2C”）总线的总线频率
公开(公告)号：US08959380B2
公开(公告)日：2015-02-17
申请号：US13467332
申请日：2012-05-09
申请人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F1/08
CPC分类号： G06F1/324 , G06F9/44 , G06F13/38 , G06F13/4282
摘要： Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.
摘要翻译：优化I2C总线频率，总线包括耦合主节点和从节点的信号线，耦合到上升时间检测电路的信号线监视信号线的电压，电压在逻辑低电平和逻辑高电平之间交替，其中优化频率包括：在信号线上升期间检测第一电压，第一电压大于逻辑低电压; 启动一个计数器，为电路的每个时钟周期增加一次; 检测信号线上的第二电压，第二电压大于第一电压并小于逻辑高电平; 停止柜台根据时钟周期和计数器值计算上升时间; 确定上升时间是否大于最大阈值; 并且如果计算的上升时间大于最大阈值，则增加I2C总线频率。

5. 发明授权

US08832538B2 Detecting data transmission errors in an inter-integrated circuit (‘I2C’) system 有权
标题翻译：检测集成电路（“I2C”）系统中的数据传输错误
公开(公告)号：US08832538B2
公开(公告)日：2014-09-09
申请号：US13530318
申请日：2012-06-22
申请人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/098 , H04L2001/0094
摘要： Detecting data transmission errors in an I2C system that includes a source device, an destination device, and a signal line coupling the I2C source and destination device, including: receiving, by the I2C destination device from the I2C source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the I2C destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the I2C source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the I2C source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.
摘要翻译：检测I2C系统中的数据传输错误，该系统包括源设备，目标设备和耦合I2C源设备和目标设备的信号线，包括：由I2C源设备从I2C源设备接收数据传输信号，数据传输信号用一组位编码; 通过I2C目的地设备检测位组中的预选位的上升时间; 如果检测到的上升时间小于预定阈值，则确定I2C源设备在信号中注入了奇偶校验位，并且如果检测到的上升时间不小于预定阈值，则确定I2C源设备未注入信号中的奇偶校验位; 以及确定所述数据传输信号是否包括与所述位组的奇偶校验有关的错误。

6. 发明授权

US09411770B2 Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select 有权
标题翻译：使用单个芯片选择来控制多个串行外设接口（“SPI”）外设
公开(公告)号：US09411770B2
公开(公告)日：2016-08-09
申请号：US13545581
申请日：2012-07-10
申请人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
发明人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F3/00 , G06F13/12 , G06F13/42
CPC分类号： G06F13/4291
摘要： Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.
摘要翻译：计算系统中使用单个芯片选择来控制多个串行外设接口（“SPI”）外围设备，所述计算系统包括SPI主机，第一SPI外设和第二SPI外设，其中第一SPI外设可操作地耦合到第二个SPI外设，包括：由第一个SPI外设接收来自SPI主机的信号; 由第一SPI外设确定第一个SPI外设是主SPI外设还是备用SPI外设; 响应于确定第一SPI外设是备用SPI外设，由第一SPI外设向第二SPI外设发送该信号; 并且响应于确定第一SPI外设是主SPI外设：由第一SPI外设处理包含在该信号中的指令; 以及由所述第一SPI外设向所述第二SPI外设发送响应信号。

7. 发明授权

US08984196B2 Accessing peripheral devices 有权
标题翻译：访问外围设备
公开(公告)号：US08984196B2
公开(公告)日：2015-03-17
申请号：US13445235
申请日：2012-04-12
申请人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
发明人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F13/00
CPC分类号： G06F13/4291
摘要： A hardware system comprises a master device and a slave device that are coupled by a signal line. A frequency generator in the master device places a selected frequency signal on the signal line. A frequency detector/comparator in the slave device, which is coupled to the signal line, determines whether the selected frequency signal on the signal line matches a predetermined frequency for the slave device. If the selected frequency signal matches the predetermined frequency, then a chip select node on the slave device is enabled, in order to permit a data exchange session between the master device and the slave device.
摘要翻译：硬件系统包括通过信号线耦合的主设备和从设备。主设备中的频率发生器将选定的频率信号放置在信号线上。耦合到信号线的从设备中的频率检测器/比较器确定信号线上选定的频率信号是否与从设备的预定频率相匹配。如果所选择的频率信号与预定频率匹配，则从设备上的片选选择节点被使能，以便允许主设备和从设备之间的数据交换会话。

8. 发明申请

US20140019644A1 Controlling A Plurality Of Serial Peripheral Interface ('SPI') Peripherals Using A Single Chip Select 有权
标题翻译：使用单片选择控制多个串行外设接口（“SPI”）外设
公开(公告)号：US20140019644A1
公开(公告)日：2014-01-16
申请号：US13545581
申请日：2012-07-10
申请人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
发明人： Michael Decesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F3/00
CPC分类号： G06F13/4291
摘要： Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.
摘要翻译：计算系统中使用单个芯片选择来控制多个串行外设接口（“SPI”）外围设备，所述计算系统包括SPI主机，第一SPI外设和第二SPI外设，其中第一SPI外设可操作地耦合到第二个SPI外设，包括：由第一个SPI外设接收来自SPI主机的信号; 由第一SPI外设确定第一个SPI外设是主SPI外设还是备用SPI外设; 响应于确定第一SPI外设是备用SPI外设，由第一SPI外设向第二SPI外设发送该信号; 并且响应于确定第一SPI外设是主SPI外设：由第一SPI外设处理包含在该信号中的指令; 以及由所述第一SPI外设向所述第二SPI外设发送响应信号。

9. 发明授权

US08819484B2 Dynamically reconfiguring a primary processor identity within a multi-processor socket server 有权
标题翻译：在多处理器套接字服务器内动态重新配置主处理器标识
公开(公告)号：US08819484B2
公开(公告)日：2014-08-26
申请号：US13268068
申请日：2011-10-07
申请人： Ralph M. Begun , Michael Decesaris , Randolph S. Kolvick , Steven L. Vanderlinden
发明人： Ralph M. Begun , Michael Decesaris , Randolph S. Kolvick , Steven L. Vanderlinden
IPC分类号： G06F11/00
CPC分类号： G06F11/1428 , G06F11/0724 , G06F11/0751
摘要： Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.
摘要翻译：提供了用于在多处理器插座服务器内动态地重新配置主处理器标识的方法，装置和计算机程序产品。实施例包括由服务处理器检测对应于第一处理器插座的处理器插座重新配置事件; 响应于检测到处理器插座重新配置事件，由服务处理器禁用服务器的第一处理器插槽; 以及由所述服务处理器将所述主处理器标识重新分配给所述服务器的第二处理器插槽。

10. 发明申请

US20130091380A1 Dynamically Reconfiguring A Primary Processor Identity Within A Multi-Processor Socket Server 有权
标题翻译：在多处理器套接字服务器中动态重新配置主处理器标识
公开(公告)号：US20130091380A1
公开(公告)日：2013-04-11
申请号：US13268068
申请日：2011-10-07
申请人： Michael Decesaris , Ralph M. Begun , Randolph S. Kolvick , Steven L. Vanderlinden
发明人： Michael Decesaris , Ralph M. Begun , Randolph S. Kolvick , Steven L. Vanderlinden
IPC分类号： G06F15/76 , G06F9/02 , G06F11/20
CPC分类号： G06F11/1428 , G06F11/0724 , G06F11/0751
摘要： Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.
摘要翻译：提供了用于在多处理器插座服务器内动态地重新配置主处理器标识的方法，装置和计算机程序产品。实施例包括由服务处理器检测对应于第一处理器插座的处理器插座重新配置事件; 响应于检测到处理器插座重新配置事件，由服务处理器禁用服务器的第一处理器插槽; 以及由所述服务处理器将所述主处理器标识重新分配给所述服务器的第二处理器插槽。

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