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1. 发明申请

US20080263330A1 Clocked ports 有权
标题翻译：时钟端口
公开(公告)号：US20080263330A1
公开(公告)日：2008-10-23
申请号：US11785345
申请日：2007-04-17
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F9/30
CPC分类号： G06F13/385 , G06F9/30032 , G06F9/3009 , G06F9/3851 , G06F13/4059 , Y02D10/14 , Y02D10/151
摘要： A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal.
摘要翻译：处理器具有接口部分和内部环境。接口部分包括至少一个端口。内部环境包括执行单元，其执行依赖于第一定时信号的指令，并根据第一定时信号在内部部分和至少一个端口之间传送数据; 以及线程调度器，用于调度由所述执行单元执行的多个线程，每个线程包括指令序列，并且所述线程调度器被配置为根据所述第一定时信号调度所述线程。端口被配置为根据第二定时信号在端口和外部环境之间传送数据，并且根据第二定时信号来改变就绪信号，以指示与外部环境的数据传输。线程调度器被配置为根据就绪信号调度一个或多个相关联的线程以执行。

2. 发明授权

US07617386B2 Scheduling thread upon ready signal set when port transfers data on trigger time activation 有权
标题翻译：当端口在触发时间激活时传输数据时，调度线程准备就绪信号设置
公开(公告)号：US07617386B2
公开(公告)日：2009-11-10
申请号：US11785346
申请日：2007-04-17
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F13/00
CPC分类号： G06F9/3851
摘要： A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time value matches the trigger time value and, provided that said match is detected, to transfer data between the port and an external environment and alter a ready signal to indicate the transfer. The internal environment comprises: an execution unit for transferring data between the at least one port and the internal environment; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions. The scheduling includes scheduling one or more of said threads for execution in dependence on the ready signal.
摘要翻译：处理器具有接口部分和内部环境。接口部分包括：布置成接收当前时间值的至少一个端口; 与端口相关联并被布置成存储触发时间值的第一寄存器; 以及比较逻辑，被配置为检测当前时间值是否与触发时间值匹配，并且如果检测到所述匹配，则在端口和外部环境之间传送数据并改变就绪信号以指示传送。内部环境包括：用于在所述至少一个端口和所述内部环境之间传送数据的执行单元; 以及线程调度器，用于调度由执行单元执行的多个线程，每个线程包括一系列指令。调度包括根据就绪信号调度用于执行的一个或多个所述线程。

3. 发明授权

US08966488B2 Synchronising groups of threads with dedicated hardware logic 有权
标题翻译：使用专用硬件逻辑同步线程组
公开(公告)号：US08966488B2
公开(公告)日：2015-02-24
申请号：US11774219
申请日：2007-07-06
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F9/46 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009
摘要： The invention provides a processor comprising an execution unit arranged to execute multiple program threads, each thread comprising a sequence of instructions, and a plurality of synchronisers for synchronising threads. Each synchroniser is operable, in response to execution by the execution unit of one or more synchroniser association instructions, to associate with a group of at least two threads. Each synchroniser is also operable, when thus associated, to synchronise the threads of the group by pausing execution of a thread in the group pending a synchronisation point in another thread of that group.
摘要翻译：本发明提供了一种处理器，其包括被执行多个程序线程的执行单元，每个线程包括指令序列，以及用于同步线程的多个同步器。响应于执行单元执行一个或多个同步器关联指令，每个同步器可操作以与一组至少两个线程相关联。当这样关联时，每个同步器也可操作，以通过暂停该组中的线程的执行以等待该组的另一个线程中的同步点来同步该组的线程。

4. 发明申请

US20090013323A1 SYNCHRONISATION 有权
标题翻译：同步
公开(公告)号：US20090013323A1
公开(公告)日：2009-01-08
申请号：US11774219
申请日：2007-07-06
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009
摘要： The invention provides a processor comprising an execution unit arranged to execute multiple program threads, each thread comprising a sequence of instructions, and a plurality of synchronisers for synchronising threads. Each synchroniser is operable, in response to execution by the execution unit of one or more synchroniser association instructions, to associate with a group of at least two threads. Each synchroniser is also operable, when thus associated, to synchronise the threads of the group by pausing execution of a thread in the group pending a synchronisation point in another thread of that group.
摘要翻译：本发明提供了一种处理器，其包括被执行多个程序线程的执行单元，每个线程包括指令序列，以及用于同步线程的多个同步器。响应于执行单元执行一个或多个同步器关联指令，每个同步器可操作以与一组至少两个线程相关联。当这样关联时，每个同步器也可操作，以通过暂停该组中的线程的执行以等待该组的另一个线程中的同步点来同步该组的线程。

5. 发明授权

US07613909B2 Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor 有权
标题翻译：恢复线程服务就绪端口以与处理器内部电路不同的时钟速率外部传输数据
公开(公告)号：US07613909B2
公开(公告)日：2009-11-03
申请号：US11785345
申请日：2007-04-17
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F13/14
CPC分类号： G06F13/385 , G06F9/30032 , G06F9/3009 , G06F9/3851 , G06F13/4059 , Y02D10/14 , Y02D10/151
摘要： A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal.
摘要翻译：处理器具有接口部分和内部环境。接口部分包括至少一个端口。内部环境包括执行单元，其执行依赖于第一定时信号的指令，并根据第一定时信号在内部部分和至少一个端口之间传送数据; 以及线程调度器，用于调度由所述执行单元执行的多个线程，每个线程包括指令序列，并且所述线程调度器被配置为根据所述第一定时信号调度所述线程。端口被配置为根据第二定时信号在端口和外部环境之间传送数据，并且根据第二定时信号来改变就绪信号，以指示与外部环境的数据传输。线程调度器被配置为根据就绪信号调度一个或多个相关联的线程以执行。

6. 发明申请

US20090013329A1 THREAD COMMUNICATIONS 有权
标题翻译：通讯
公开(公告)号：US20090013329A1
公开(公告)日：2009-01-08
申请号：US11774315
申请日：2007-07-06
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F13/00
CPC分类号： G06F9/30072 , G06F9/30087 , G06F9/3009 , G06F9/30123 , G06F9/3851
摘要： The invention relates to a device comprising a processor, the processor comprising: an execution unit for executing multiple threads, each thread comprising a sequence of instructions; and a plurality of sets of thread registers, each set arranged to store information relating to a respective one of the plurality of threads. The processor also comprises circuitry for establishing channels between thread register sets, the circuitry comprising a plurality of channel terminals and being operable to establish a channel between one of the thread register sets and another thread register set via one of the channel terminals and another channel terminal. Each channel terminal comprises at least one buffer operable to buffer data transferred over a thus established channel and a channel terminal identifier register operable to store an identifier of the other channel terminal via which that channel is established.
摘要翻译：本发明涉及一种包括处理器的设备，所述处理器包括：用于执行多个线程的执行单元，每个线程包括指令序列; 以及多组线程寄存器，每组线程寄存器被设置为存储与多个线程中的相应一个线程有关的信息。处理器还包括用于在线程寄存器组之间建立通道的电路，该电路包括多个通道终端，并且可操作以在线程寄存器组中的一个和经由一个通道终端设置的另一个线程寄存器之间建立通道，另一个通道终端。每个信道终端包括至少一个缓冲器，用于缓冲通过这样建立的信道传输的数据;以及信道终端标识符寄存器，其可操作以存储建立该信道的另一信道终端的标识符。

7. 发明授权

US08347312B2 Thread communications 有权
标题翻译：线程通信
公开(公告)号：US08347312B2
公开(公告)日：2013-01-01
申请号：US11774315
申请日：2007-07-06
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F9/30072 , G06F9/30087 , G06F9/3009 , G06F9/30123 , G06F9/3851
摘要： The invention relates to a device comprising a processor, the processor comprising: an execution unit for executing multiple threads, each thread comprising a sequence of instructions; and a plurality of sets of thread registers, each set arranged to store information relating to a respective one of the plurality of threads. The processor also comprises circuitry for establishing channels between thread register sets, the circuitry comprising a plurality of channel terminals and being operable to establish a channel between one of the thread register sets and another thread register set via one of the channel terminals and another channel terminal. Each channel terminal comprises at least one buffer operable to buffer data transferred over a thus established channel and a channel terminal identifier register operable to store an identifier of the other channel terminal via which that channel is established.
摘要翻译：本发明涉及一种包括处理器的设备，所述处理器包括：用于执行多个线程的执行单元，每个线程包括指令序列; 以及多组线程寄存器，每组线程寄存器被设置为存储与多个线程中的相应一个线程有关的信息。处理器还包括用于在线程寄存器组之间建立通道的电路，该电路包括多个通道终端，并且可操作以在线程寄存器组中的一个和经由一个通道终端设置的另一个线程寄存器之间建立通道，另一个通道终端。每个信道终端包括至少一个缓冲器，用于缓冲通过这样建立的信道传输的数据;以及信道终端标识符寄存器，其可操作以存储建立该信道的另一信道终端的标识符。

8. 发明申请

US20080263318A1 Timed ports 有权
标题翻译：定时港口
公开(公告)号：US20080263318A1
公开(公告)日：2008-10-23
申请号：US11785346
申请日：2007-04-17
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F15/00
CPC分类号： G06F9/3851
摘要： A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time value matches the trigger time value and, provided that said match is detected, to transfer data between the port and an external environment and alter a ready signal to indicate the transfer. The internal environment comprises: an execution unit for transferring data between the at least one port and the internal environment; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions. The scheduling includes scheduling one or more of said threads for execution in dependence on the ready signal.
摘要翻译：处理器具有接口部分和内部环境。接口部分包括：布置成接收当前时间值的至少一个端口; 与端口相关联并被布置成存储触发时间值的第一寄存器; 以及比较逻辑，被配置为检测当前时间值是否与触发时间值匹配，并且如果检测到所述匹配，则在端口和外部环境之间传送数据并改变就绪信号以指示传送。内部环境包括：用于在所述至少一个端口和所述内部环境之间传送数据的执行单元; 以及线程调度器，用于调度由执行单元执行的多个线程，每个线程包括一系列指令。调度包括根据就绪信号调度用于执行的一个或多个所述线程。

9. 发明申请

US20050278510A1 Pseudo register file write ports 审中-公开
标题翻译：伪寄存器文件写入端口
公开(公告)号：US20050278510A1
公开(公告)日：2005-12-15
申请号：US11127779
申请日：2005-05-12
申请人： Kristen Jacobs , Peter Hedinger
发明人： Kristen Jacobs , Peter Hedinger
IPC分类号： G06F9/30 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3824 , G06F9/30141
摘要： A system comprising execution circuitry for executing instructions and a register file comprising at least one port, the circuitry operating to allow said execution circuitry to share a common port of said register file.
摘要翻译：一种包括用于执行指令的执行电路和包括至少一个端口的寄存器文件的系统，所述电路用于允许所述执行电路共享所述寄存器文件的公共端口。

10. 发明授权

US06883067B2 Evaluation and optimization of code 有权
标题翻译：代码的评估和优化
公开(公告)号：US06883067B2
公开(公告)日：2005-04-19
申请号：US10072814
申请日：2002-02-08
申请人： Trefor Southwell , Peter Hedinger , Kristen Jacobs
发明人： Trefor Southwell , Peter Hedinger , Kristen Jacobs
IPC分类号： G06F9/45 , G06F12/00 , G06F12/08
CPC分类号： G06F8/4442
摘要： A memory map evaluation tool is provided that organizes a program in a manner most compatible with use of a cache. The tool includes a method that involves executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.
摘要翻译：提供了以与缓存的使用最相容的方式组织程序的存储器映射评估工具。该工具包括一种方法，其涉及根据第一存储器映射执行程序的第一版本以生成程序计数器跟踪，将程序计数器跟踪转换为特定格式，然后使用存储器映射将程序计数器跟踪转换为物理地址被评估，不同于第一个存储器映射。然后，这些物理地址用于使用正在评估的内存映射的直接映射高速缓存的模型来评估可能的高速缓存未命中的数量。

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