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1. 发明授权

US07170512B2 Index processor 有权
标题翻译：索引处理器
公开(公告)号：US07170512B2
公开(公告)日：2007-01-30
申请号：US10133971
申请日：2002-04-26
申请人： Trefor Southwell , Magne Sandven
发明人： Trefor Southwell , Magne Sandven
IPC分类号： G06T17/00
CPC分类号： G06T15/005
摘要： A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.
摘要翻译：一种具有索引处理单元的图形处理器，用于预处理构成三维图像的顶点列表。预处理方法包括以下步骤。首先，将三维图像分解为由一组顶点定义的多个基元，每个顶点包含存储在顶点存储区域中并且可由顶点索引寻址的顶点信息。然后接收所述顶点索引并创建一组唯一索引，其识别一批顶点，并仅将与所述唯一索引对应的顶点加载到顶点存储区域中。最后使用独特的索引从顶点存储区域中寻址的变换顶点信息创建变换的原始元素。

2. 发明授权

US06883067B2 Evaluation and optimization of code 有权
标题翻译：代码的评估和优化
公开(公告)号：US06883067B2
公开(公告)日：2005-04-19
申请号：US10072814
申请日：2002-02-08
申请人： Trefor Southwell , Peter Hedinger , Kristen Jacobs
发明人： Trefor Southwell , Peter Hedinger , Kristen Jacobs
IPC分类号： G06F9/45 , G06F12/00 , G06F12/08
CPC分类号： G06F8/4442
摘要： A memory map evaluation tool is provided that organizes a program in a manner most compatible with use of a cache. The tool includes a method that involves executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.
摘要翻译：提供了以与缓存的使用最相容的方式组织程序的存储器映射评估工具。该工具包括一种方法，其涉及根据第一存储器映射执行程序的第一版本以生成程序计数器跟踪，将程序计数器跟踪转换为特定格式，然后使用存储器映射将程序计数器跟踪转换为物理地址被评估，不同于第一个存储器映射。然后，这些物理地址用于使用正在评估的内存映射的直接映射高速缓存的模型来评估可能的高速缓存未命中的数量。

3. 发明申请

US20050013183A1 Load control 有权
标题翻译：负载控制
公开(公告)号：US20050013183A1
公开(公告)日：2005-01-20
申请号：US10830717
申请日：2004-04-23
申请人： Trefor Southwell
发明人： Trefor Southwell
IPC分类号： G06F9/38 , G06F12/14 , G11C7/00
CPC分类号： G06F12/145 , G06F9/3842 , G06F9/3861 , G06F12/1441
摘要： A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load control unit is used to define a plurality of memory regions and has means for checking whether the physical addresses lie within at least one of said defined memory regions. In this way, the control unit allows the mapping of large physical page size to RAM devices and the extra address space is filtered off by the control unit so that speculative loads are not carried out in unknown regions.
摘要翻译：一种用于验证投机负载操作的方法和系统。该系统识别可能在代码序列中执行的推测加载操作，并且在将推测负载的虚拟地址转换为物理地址之后，推测负载控制单元用于定义多个存储器区域，并且具有用于检查是否物理地址位于所述定义的存储区域的至少一个内。以这种方式，控制单元允许将大的物理页面大小映射到RAM设备，并且由控制单元滤除额外的地址空间，以便在未知区域中不执行推测负载。

4. 发明授权

US07216342B2 Code generation 有权
标题翻译：代码生成
公开(公告)号：US07216342B2
公开(公告)日：2007-05-08
申请号：US10099455
申请日：2002-03-14
申请人： Trefor Southwell , Peter Hedinger
发明人： Trefor Southwell , Peter Hedinger
IPC分类号： G06F9/44
CPC分类号： G06F12/126 , G06F8/54
摘要： A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.
摘要翻译：一种链接多个对象文件以生成可执行程序的方法，所述方法包括在执行程序时在目标文件中识别要被锁定到高速缓存中的至少一个例程，将所述例程定位在一组存储器地址到一组缓存位置，并将映射到同一组高速缓存位置的其他存储器地址集合引入可执行程序间隙。

5. 发明授权

US07062634B1 Processor and a method for handling and encoding no-operation instructions 有权
标题翻译：处理器和处理和编码无操作指令的方法
公开(公告)号：US07062634B1
公开(公告)日：2006-06-13
申请号：US10060070
申请日：2002-01-29
申请人： Trefor Southwell , Peter Hedinger
发明人： Trefor Southwell , Peter Hedinger
IPC分类号： G06F15/00
CPC分类号： G06F9/3822 , G06F9/30156 , G06F9/3853
摘要： A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions.
摘要翻译：描述了一种处理器，其中通过提供用于响应于在操作指令中编码的信息而产生nops的设备来最小化对程序中的无操作指令（nop）进行编码的需要。

6. 发明授权

US06959363B2 Cache memory operation 有权
标题翻译：缓存内存操作
公开(公告)号：US06959363B2
公开(公告)日：2005-10-25
申请号：US10278772
申请日：2002-10-22
申请人： Trefor Southwell , Peter Hedinger
发明人： Trefor Southwell , Peter Hedinger
IPC分类号： G06F12/0862 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/1024 , G06F2212/502 , G06F2212/6026
摘要： A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.
摘要翻译：高速缓存存储器包括：提取引擎，被配置为发出用于从正在执行的程序中的访问地址识别的主存储器中的位置访问数据项的提取请求，控制的预取引擎发布用于推测访问预取的预取请求来自所述主存储器中的位置的数据项，其由被确定为来自所述访问地址的相应位置的位置的数量确定;以及校准器，被配置为选择性地改变所述位置数。

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