专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4888689A Apparatus and method for improving cache access throughput in pipelined processors 失效
标题翻译：用于提高流水线处理器中缓存访问吞吐量的装置和方法
公开(公告)号：US4888689A
公开(公告)日：1989-12-19
申请号：US920805
申请日：1986-10-17
申请人： Michael D. Taylor , Robert M. Maier , Michael J. Begley , Allan J. Zmyslowski , Jeffrey A. Thomas , Joseph A. Petolino
发明人： Michael D. Taylor , Robert M. Maier , Michael J. Begley , Allan J. Zmyslowski , Jeffrey A. Thomas , Joseph A. Petolino
IPC分类号： G06F9/38
CPC分类号： G06F9/383
摘要： An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.
摘要翻译：如果联锁指令可能需要存储单元管理工作，则用于在指令流水线的互锁期间用于提高高速缓存存储单元利用率的装置和方法在互锁的一个周期期间生成控制信号。响应于控制信号，存储单元中的选择器控制逻辑产生指示由存储单元进行选择的互锁指令的优先信号进行处理。响应于控制信号和优先级信号，在互锁指令的互锁期间使用高速缓存管理逻辑来准备在互锁被释放时提供所需数据。

2. 发明授权

US4851993A Cache move-in bypass 失效
标题翻译：缓存移入旁路
公开(公告)号：US4851993A
公开(公告)日：1989-07-25
申请号：US41046
申请日：1987-04-20
申请人： Jack Chen , Jeffrey A. Thomas , Joseph A. Petolino, Jr. , Michael J. Begley , Ajay Shah , Michael D. Taylor , Richard J. Tobias
发明人： Jack Chen , Jeffrey A. Thomas , Joseph A. Petolino, Jr. , Michael J. Begley , Ajay Shah , Michael D. Taylor , Richard J. Tobias
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F12/0855 , G06F12/0888 , G06F9/3826
摘要： Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.
摘要翻译：将数据从主存储单元旁路到中间存储单元周围的指令和操作数处理单元，提高了数据处理系统的性能。指令和操作数处理单元向中间存储单元或高速缓存提供对操作数的请求。如果从缓存中缺少该行，则从主存储单元检索请求操作数。旁路数据路径连接在主存储单元之前，在高速缓存中的错误检测装置之前，以及用于将请求的操作数直接传送到指令和操作数处理单元的指令和操作数处理单元。控制，耦合以接收对操作数的请求以及指令和操作数处理单元的信号，指示和操作数处理单元在数据包括请求的操作数时从旁路数据路径接收所请求的操作数。

3. 发明授权

US4722046A Cache storage priority 失效
标题翻译：缓存存储优先级
公开(公告)号：US4722046A
公开(公告)日：1988-01-26
申请号：US920803
申请日：1986-10-17
申请人： Mehrzad Kasrazadeh , Michael D. Taylor , Jeffrey A. Thomas , Christopher D. Finan , Joseph A. Petolino
发明人： Mehrzad Kasrazadeh , Michael D. Taylor , Jeffrey A. Thomas , Christopher D. Finan , Joseph A. Petolino
IPC分类号： G06F9/38 , G06F12/08 , G06F13/14
CPC分类号： G06F12/0855 , G06F12/0804 , G06F9/3824
摘要： A data processing machine includes an instruction unit that decodes and organizes a flow of instructions for processing data. In response to certain instructions, the instruction unit generates requests for storage unit resources. In addition, results generated in the instruction unit in response to certain instructions are supplied for storage in the storage unit. The storage unit selects in response to priority logic from completing requests for storage unit resources, including a high speed cache storing data, and a plurality of storage ports for transferring data from the result register to the high speed cache. Each of the storage ports generates requests for access to the high speed cache to transfer the data stored in the respective store ports to the cache. Storage unit priority is determined in part by predicting the fullness of the storage ports.
摘要翻译：数据处理机包括指令单元，其对用于处理数据的指令流进行解码和组织。响应于某些指令，指令单元产生对存储单元资源的请求。此外，响应于某些指令在指令单元中产生的结果被提供用于存储在存储单元中。存储单元响应于优先级逻辑来选择完成对存储单元资源的请求，包括存储数据的高速缓存以及用于将数据从结果寄存器传送到高速缓存的多个存储端口。每个存储端口产生访问高速缓存的请求，以将存储在各个存储端口中的数据传送到高速缓存。存储单元优先级部分通过预测存储端口的丰满度来确定。

4. 发明授权

US4855904A Cache storage queue 失效
标题翻译：缓存存储队列
公开(公告)号：US4855904A
公开(公告)日：1989-08-08
申请号：US225875
申请日：1988-09-22
申请人： Kevin L. Daberkow , Christopher D. Finan , Joseph A. Petolino , Daniel C. Sobottka , Jeffrey A. Thomas
发明人： Kevin L. Daberkow , Christopher D. Finan , Joseph A. Petolino , Daniel C. Sobottka , Jeffrey A. Thomas
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3824 , G06F12/0855
摘要： In a pipeline data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results including data and address information of a flow of the first pipeline, the present invention provides an apparatus for transferring results in the result register to the second unit. A plurality of registers connected to the result register, each storing the result from at least one flow of the first pipeline and storing control information is provided. Further, a controller in communication with the second unit and the plurality of ports responsive to the control information and a flow of the second pipeline is included for selecting one of the plurality of ports in a first-in, first-out queue as a port to the second unit and for updating the control information.
摘要翻译：在具有用于执行根据第一流水线运行的指令的第一单元和用于存储根据第二流水线运行的多个端口的数据的地址单元的流水线数据处理机中，所述第一单元具有用于保存结果的结果寄存器，包括第一流水线的数据和地址信息，本发明提供一种用于将结果寄存器中的结果传送到第二单元的装置。提供连接到结果寄存器的多个寄存器，每个寄存器存储来自第一流水线的至少一个流的结果和存储控制信息。此外，包括响应于控制信息和第二流水线的与第二单元和多个端口通信的控制器，用于在先入先出的队列中选择多个端口中的一个作为端口到第二单元并用于更新控制信息。

5. 发明授权

US4872111A Monolithic semi-custom IC having standard LSI sections and coupling gate array sections 失效
标题翻译：具有标准LSI部分和耦合门阵列部分的单片半定制IC
公开(公告)号：US4872111A
公开(公告)日：1989-10-03
申请号：US233953
申请日：1988-08-18
申请人： Kevin L. Daberkow , Christopher D. Finan , Joseph A. Petolino , Daniel Carl Sobottka , Jeffrey A. Thomas
发明人： Kevin L. Daberkow , Christopher D. Finan , Joseph A. Petolino , Daniel Carl Sobottka , Jeffrey A. Thomas
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F12/0855 , G06F9/3824
摘要： In a data processing system including a pipelined instruction execution unit and a pipelined high speed cache, a storage queue consisting of a set of FIFO registers and associated support logic handles transfer of data from the pipeline instruction execution unit to the high speed cache. When a store request flow from the instruction execution pipeline is forwarded to the high speed cache, instead of placing the data directly into the high speed cache, the starting address, length of store and data to be stored are placed into one of the store queue registers. The instruction execution unit sees the store request as completed and continues processing even though data has not been physically placed in the high speed cache. The write to the high speed cache is finished in the background at a later time during an unused storage pipeline cycle in the high speed cache.
摘要翻译：在包括流水线指令执行单元和流水线高速缓存的数据处理系统中，由一组FIFO寄存器和相关联的支持逻辑组成的存储队列将数据从流水线指令执行单元传送到高速缓存。当来自指令执行流水线的存储请求流被转发到高速缓存时，代替将数据直接放入高速缓存中，将存储的起始地址，存储长度和要存储的数据放入存储队列之一注册指令执行单元将存储请求视为已完成，并且即使数据尚未物理放置在高速缓存中也继续处理。在高速缓存中的未使用的存储管线周期期间的后续时间内，对高速缓存的写入完成。

6. 发明授权

US4852100A Error detection and correction scheme for main storage unit 失效
标题翻译：主存储单元的错误检测和纠正方案
公开(公告)号：US4852100A
公开(公告)日：1989-07-25
申请号：US61847
申请日：1987-06-11
申请人： Harold F. Christensen , Jeffrey A. Thomas , Jeffrey Isozaki , Joseph A. Petolino
发明人： Harold F. Christensen , Jeffrey A. Thomas , Jeffrey Isozaki , Joseph A. Petolino
IPC分类号： G06F11/07 , G06F11/10 , G06F12/00
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/10 , G06F12/00
摘要： The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing said multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting said multiple digital first signals substantially from said first means to said second means; fourth means for providing said at least one digital second signal, in the course of the transmitting of said first signals by said third means, in response to an occurrence of one or more errors in one or more of said multiple digital first signals; fifth means for transmitting said multiple digital first signals substantially from said second means to said first means; and sixth means adapted for receiving said at least one digital second signal in the course of the transmitting of said multiple digital first signals by said fifth means and for providing at least one third signal in response to an occurrence of said at least one digital second signal. ECC codes are generated and applied over a plurality of distinct checking blocks in each flow of data in order to minimize delays in the move-in data path, and bypass data paths are provided such that a flow may bypass all error checking and correcting circuitry and cacheing apparatus between the main storage array and the CPU.
摘要翻译：本发明提供一种用于报告存储在数据处理器的存储装置中的数据中的错误的装置，包括：用于存储多个数字第一信号的第一装置; 用于存储所述多个数字第一信号并适于存储至少一个数字第二信号的第二装置; 用于将所述多个数字第一信号基本上从所述第一装置发送到所述第二装置的第三装置; 第四装置，用于在所述第三装置发送所述第一信号的过程中，响应于在所述多个数字第一信号中的一个或多个中出现一个或多个错误，提供所述至少一个数字第二信号; 用于将所述多个数字第一信号基本上从所述第二装置发送到所述第一装置的第五装置; 以及第六装置，适于在所述第五装置发送所述多个数字第一信号的过程中接收所述至少一个数字第二信号，并响应于所述至少一个数字第二信号的发生而提供至少一个第三信号。在每个数据流中，通过多个不同的检查块生成并应用ECC代码，以便最小化移入数据路径中的延迟，并且提供旁路数据路径，使得流可绕过所有错误检查和校正电路，并且主存储阵列与CPU之间的缓存设备。

7. 发明授权

US5095424A Computer system architecture implementing split instruction and operand cache line-pair-state management 失效
标题翻译：计算机系统架构实现分割指令和操作数高速缓存线对状态管理
公开(公告)号：US5095424A
公开(公告)日：1992-03-10
申请号：US384867
申请日：1989-07-21
申请人： Gary A. Woffinden , Theodore S. Robinson , Jeffrey A. Thomas , Robert A. Ertl , James P. Millar , Christopher D. Finan , Joseph A. Petolino , Ajay Shah , Shen H. Wang , Mark Semmelmeyer
发明人： Gary A. Woffinden , Theodore S. Robinson , Jeffrey A. Thomas , Robert A. Ertl , James P. Millar , Christopher D. Finan , Joseph A. Petolino , Ajay Shah , Shen H. Wang , Mark Semmelmeyer
IPC分类号： G06F12/08
CPC分类号： G06F12/0848
摘要： A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.
摘要翻译：描述了实现多个中央处理单元的计算机系统架构，每个中央处理单元包括分割指令和操作数高速缓存，并且通过使用线对状态来管理存储器线的多个副本（线对）。当对指令和操作数数据高速缓存存储器进行传输时，对存储器线路的系统管理允许始终保持系统的完整性。分割高速缓存架构管理确定在指令和操作数高速缓存存储器内是否存在具有第一预定系统地址的存储器线，或者将在存储器线路中移入。维持地址标签线对状态信息以允许确定各个存储器线对成员是否存在和在何处驻留。该架构在将存储器线路的每次传送到系统的任何分割高速缓存时实现线对的管理。只要在单个中央处理器的每个指令和操作数缓存缓冲器中的相同相对位置存在相同的存储器线，就允许线对存在。该架构还包括数据路径选择器，用于根据操作数缓冲目标是作为线对的成员的存储线，将操作数数据传送到指令或操作数数据高速缓冲存储器或两者。

8. 发明授权

US06391403B1 Zeolite in packaging film 失效
公开(公告)号：US06391403B1
公开(公告)日：2002-05-21
申请号：US09691570
申请日：2000-10-18
申请人： Thomas A. Blinka , Frank B. Edwards , Nathanael R. Miranda , Drew V. Speer , Jeffrey A. Thomas
发明人： Thomas A. Blinka , Frank B. Edwards , Nathanael R. Miranda , Drew V. Speer , Jeffrey A. Thomas
IPC分类号： B32B2704
CPC分类号： B32B27/18 , A61L33/068 , B32B27/08 , B32B2439/00 , B32B2581/00 , C08G83/007 , C08K3/36 , C08K5/0008 , C08L71/02 , Y10T428/131 , Y10T428/1334 , Y10T428/1341 , Y10T428/1352 , Y10T428/1355 , Y10T428/1359 , Y10T428/1379 , Y10T428/1397 , Y10T428/249956 , Y10T428/2813 , Y10T428/2826 , Y10T428/31855 , Y10T428/31909 , Y10T428/31913 , C08L23/04 , C08L2666/26
摘要： An article of manufacture includes an oxygen scavenger and a zeolite. The article can be in the form of e.g. a film or sealing compound. A package can be made from the article for containing an oxygen-sensitive article such as food. The zeolite reduces migration of odor causing by-products of the oxygen scavenging process. A method of making an article of manufacture having reduced migration of by-products of an oxygen scavenging reaction includes providing an article including an oxygen scavenger and a zeolite; and exposing the article to actinic radiation.

9. 发明授权

US06233907B1 Method and apparatus for triggering oxygen scavenging material as a wall component in a container 失效
标题翻译：用于将氧气清除材料作为容器中的壁组分触发的方法和装置
公开(公告)号：US06233907B1
公开(公告)日：2001-05-22
申请号：US09230595
申请日：1999-06-24
申请人： Philip H. Cook, Jr. , Michael J. Carey , Jeffrey A. Thomas , Nathanael R. Miranda
发明人： Philip H. Cook, Jr. , Michael J. Carey , Jeffrey A. Thomas , Nathanael R. Miranda
IPC分类号： B65D8124
CPC分类号： B65D81/267
摘要： A method for triggering an oxygen scavenging component of a container for packaging an oxygen sensitive material includes the steps of providing a container defining an internal space and having an internal oxygen scavenging component including an oxidizable organic compound, exposing the oxygen scavenging component to a source of actinic radiation, positioned within said internal space, at a wavelength, intensity, and residence time so as to provide a dose of actinic radiation sufficient to activate the oxygen scavenging component, and packaging an oxygen sensitive material in the internal space of the container whereby the oxygen scavenging component scavenges the oxygen from the internal space of the container. An apparatus and packaging system are also disclosed.
摘要翻译：触发用于包装氧敏感材料的容器的除氧组分的方法包括以下步骤：提供限定内部空间并具有包含可氧化有机化合物的内部氧清除组分的容器，将氧清除组分暴露于光化辐射，位于所述内部空间内，以波长，强度和停留时间，以提供足以激活除氧组分的光化辐射剂量，以及将氧敏感材料包装在容器的内部空间中，由此，除氧组分清除容器内部空间的氧气。还公开了一种装置和包装系统。

10. 发明授权

US06209800B1 Watering system 失效
标题翻译：浇水系统
公开(公告)号：US06209800B1
公开(公告)日：2001-04-03
申请号：US09377853
申请日：1999-08-20
申请人： Jeffrey A. Thomas
发明人： Jeffrey A. Thomas
IPC分类号： B05B901
CPC分类号： F16L11/12 , F16L11/04
摘要： A garden watering system including an elongate flexible tube formed in extendable and contractible helical coils having opposed ends, with a faucet connector attached to one end of the tube, and a spray nozzle or wand connected to the opposite end of the tube. The coiled tube permits a wide range of extension of the watering system during use.
摘要翻译：一种花园浇水系统，其包括细长柔性管，其形成为具有相对端部的可伸缩和螺旋形线圈，其中连接到所述管的一端的水龙头连接器，以及连接到所述管的相对端的喷嘴或棒。卷取管允许在使用期间浇水系统的广泛范围的延伸。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式