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1. 发明授权

US4855904A Cache storage queue 失效
标题翻译：缓存存储队列
公开(公告)号：US4855904A
公开(公告)日：1989-08-08
申请号：US225875
申请日：1988-09-22
申请人： Kevin L. Daberkow , Christopher D. Finan , Joseph A. Petolino , Daniel C. Sobottka , Jeffrey A. Thomas
发明人： Kevin L. Daberkow , Christopher D. Finan , Joseph A. Petolino , Daniel C. Sobottka , Jeffrey A. Thomas
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3824 , G06F12/0855
摘要： In a pipeline data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results including data and address information of a flow of the first pipeline, the present invention provides an apparatus for transferring results in the result register to the second unit. A plurality of registers connected to the result register, each storing the result from at least one flow of the first pipeline and storing control information is provided. Further, a controller in communication with the second unit and the plurality of ports responsive to the control information and a flow of the second pipeline is included for selecting one of the plurality of ports in a first-in, first-out queue as a port to the second unit and for updating the control information.
摘要翻译：在具有用于执行根据第一流水线运行的指令的第一单元和用于存储根据第二流水线运行的多个端口的数据的地址单元的流水线数据处理机中，所述第一单元具有用于保存结果的结果寄存器，包括第一流水线的数据和地址信息，本发明提供一种用于将结果寄存器中的结果传送到第二单元的装置。提供连接到结果寄存器的多个寄存器，每个寄存器存储来自第一流水线的至少一个流的结果和存储控制信息。此外，包括响应于控制信息和第二流水线的与第二单元和多个端口通信的控制器，用于在先入先出的队列中选择多个端口中的一个作为端口到第二单元并用于更新控制信息。

2. 发明授权

US4872111A Monolithic semi-custom IC having standard LSI sections and coupling gate array sections 失效
标题翻译：具有标准LSI部分和耦合门阵列部分的单片半定制IC
公开(公告)号：US4872111A
公开(公告)日：1989-10-03
申请号：US233953
申请日：1988-08-18
申请人： Kevin L. Daberkow , Christopher D. Finan , Joseph A. Petolino , Daniel Carl Sobottka , Jeffrey A. Thomas
发明人： Kevin L. Daberkow , Christopher D. Finan , Joseph A. Petolino , Daniel Carl Sobottka , Jeffrey A. Thomas
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F12/0855 , G06F9/3824
摘要： In a data processing system including a pipelined instruction execution unit and a pipelined high speed cache, a storage queue consisting of a set of FIFO registers and associated support logic handles transfer of data from the pipeline instruction execution unit to the high speed cache. When a store request flow from the instruction execution pipeline is forwarded to the high speed cache, instead of placing the data directly into the high speed cache, the starting address, length of store and data to be stored are placed into one of the store queue registers. The instruction execution unit sees the store request as completed and continues processing even though data has not been physically placed in the high speed cache. The write to the high speed cache is finished in the background at a later time during an unused storage pipeline cycle in the high speed cache.
摘要翻译：在包括流水线指令执行单元和流水线高速缓存的数据处理系统中，由一组FIFO寄存器和相关联的支持逻辑组成的存储队列将数据从流水线指令执行单元传送到高速缓存。当来自指令执行流水线的存储请求流被转发到高速缓存时，代替将数据直接放入高速缓存中，将存储的起始地址，存储长度和要存储的数据放入存储队列之一注册指令执行单元将存储请求视为已完成，并且即使数据尚未物理放置在高速缓存中也继续处理。在高速缓存中的未使用的存储管线周期期间的后续时间内，对高速缓存的写入完成。

3. 发明授权

US06341324B1 Exception processing in superscalar microprocessor 失效
标题翻译：超标量微处理器异常处理
公开(公告)号：US06341324B1
公开(公告)日：2002-01-22
申请号：US08540349
申请日：1995-10-06
申请人： Robert L. Caulk, Jr. , Hidetaka Magoshi , Kevin L. Daberkow
发明人： Robert L. Caulk, Jr. , Hidetaka Magoshi , Kevin L. Daberkow
IPC分类号： G06F1300
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3861 , G06F9/3885
摘要： A microprocessor system includes a core CPU for instruction execution and a coprocessor interconnected with said core CPU for system control and exception processing. The coprocessor includes a plurality of exception handling registers including an exception program counter having a restart location stored therein for use after an exception is serviced, a status register having operating mode identification and interrupt enabling bits, and a configuration and cache control register. Interrupt processing is compatible with a plurality of instruction sets with a particular instruction set being designated by setting at least one bit in the configuration and cache control register. Registers are provided to save the operating state of the CPU prior to interrupt enable, the operating state of the CPU being restored after exception processing is completed and user mode is reestablished.
摘要翻译：微处理器系统包括用于指令执行的核心CPU和与所述核心CPU相互连接的用于系统控制和异常处理的协处理器。协处理器包括多个异常处理寄存器，其包括异常程序计数器，该异常程序计数器具有存储在其中的重新启动位置，用于在异常被服务之后使用，具有操作模式识别和中断使能位的状态寄存器以及配置和高速缓存控制寄存器。中断处理与通过设置配置和高速缓存控制寄存器中的至少一个比特指定的特定指令集的多个指令集兼容。提供寄存器以在中断使能之前保存CPU的工作状态，在完成异常处理并重新建立用户模式后恢复CPU的运行状态。

4. 发明授权

US5016167A Resource contention deadlock detection and prevention 失效
标题翻译：资源争用死锁检测和预防
公开(公告)号：US5016167A
公开(公告)日：1991-05-14
申请号：US135845
申请日：1987-12-21
申请人： Kham X. Nguyen , Theodore S. Robinson , Michael D. Taylor , Kevin L. Daberkow
发明人： Kham X. Nguyen , Theodore S. Robinson , Michael D. Taylor , Kevin L. Daberkow
IPC分类号： G06F9/46 , G06F13/376 , G06F15/17 , G06F15/173
CPC分类号： G06F9/524 , G06F13/376 , G06F15/17 , G06F15/173
摘要： In a multiprocessor system with an interleaved memory, predicted busy terms for interleaves of the main store being accessed are sent to each processor in the system, so that they will not waste pipe flows making requests to the busy interleaves. The predicted busy term is lowered before access to the interleaves is complete, to allow for the latency between the time the processor sets up the request and the time the main store system receives it. Contention occurs when several processors request access to the same interleave of main store. To detect deadlocks, a counter for each processor keeps track of the number of consecutive requests from that processor which have been rejected. Once the number reaches a threshold for a first processor, its counter initiates a state machine which inhibits other processors from making requests to the main store until the first processor is successful in gaining access.
摘要翻译：在具有交错存储器的多处理器系统中，被访问的主存储器的交织的预测繁忙项被发送到系统中的每个处理器，使得它们不会浪费向繁忙交错提出请求的管道流。在访问交错完成之前，预测的繁忙字词被降低，以允许处理器设置请求的时间与主存储系统接收时间之间的延迟。当几个处理器请求访问主存储的相同交错时，会发生争用。为了检测死锁，每个处理器的计数器跟踪已被拒绝的处理器的连续请求数。一旦数量达到第一处理器的阈值，其计数器启动一个状态机，禁止其他处理器向主存储器发出请求，直到第一个处理器成功访问。

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