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1. 发明授权

US5708659A Method for hashing in a packet network switching system 失效
标题翻译：分组网络交换系统中的散列方法
公开(公告)号：US5708659A
公开(公告)日：1998-01-13
申请号：US389601
申请日：1995-02-16
申请人： Michael D. Rostoker , John P. Daane , Sanjay M. Desai , Anthony Stelliga
发明人： Michael D. Rostoker , John P. Daane , Sanjay M. Desai , Anthony Stelliga
IPC分类号： G06F13/12 , H04L12/26 , H04L12/56 , H04N5/00 , H04N7/24 , H04N7/26 , H04N7/50 , H04Q11/04 , H04L12/66
CPC分类号： G06F13/128 , H04L12/2602 , H04L12/5602 , H04L43/00 , H04L45/745 , H04L47/10 , H04L47/11 , H04L47/263 , H04L49/3081 , H04L49/355 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L49/9063 , H04L49/9078 , H04N19/00 , H04N19/42 , H04N19/61 , H04N21/2381 , H04N21/4143 , H04N21/437 , H04N21/4381 , H04N21/4385 , H04N21/4788 , H04N21/6402 , H04N21/64307 , H04Q11/0478 , H04L2012/5613 , H04L2012/5614 , H04L2012/5616 , H04L2012/5628 , H04L2012/5632 , H04L2012/5635 , H04L2012/5636 , H04L2012/5637 , H04L2012/5638 , H04L2012/5647 , H04L2012/5652 , H04L2012/5653 , H04L2012/5664 , H04L43/0817 , H04L43/0852 , H04L43/10 , H04L43/106 , H04L49/20 , H04L49/25 , H04L49/30 , H04L49/3009 , H04L49/505 , H04N19/70 , H04Q2213/13034 , H04Q2213/13097 , H04Q2213/13141 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/13216 , H04Q2213/13296 , H04Q2213/13322 , H04Q2213/13332 , H04Q2213/13353
摘要： The port in a packet network switching system that a packet should be associated with is determined by retrieving packet address information for a packet that is to be transmitted. A predetermined number of bits from the packet address information is selected to use a hash key, which is used to compute a table address. The contents of the table at that address are compared with the packet address information. If it matches, the packet is transmitted over the port associated with that particular destination address. If it does not match, the table address is incremented by one, and the contents of the new table location identified by the incremented address are compared with the packet address information. A high speed digital video network apparatus which utilizes the hashing function is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits.
摘要翻译：通过检索要发送的分组的分组地址信息来确定分组应该关联的分组网络交换系统中的端口。选择来自分组地址信息的预定数量的比特以使用用于计算表地址的哈希密钥。将该地址表中的内容与数据包地址信息进行比较。如果匹配，则通过与该特定目的地址相关联的端口发送分组。如果不匹配，则表地址增加1，并将由递增地址标识的新表位置的内容与分组地址信息进行比较。利用散列功能的高速数字视频网络设备在单个集成电路芯片上实现，并且包括网络协议处理系统互连，压缩/解压缩电路和编码器/解码器电路。

2. 发明授权

US5856975A High speed single chip digital video network apparatus 失效
标题翻译：高速单片机数字视频网络设备
公开(公告)号：US5856975A
公开(公告)日：1999-01-05
申请号：US354682
申请日：1994-12-08
申请人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
发明人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
IPC分类号： H04Q3/00 , G06F13/12 , H04L12/26 , H04L12/56 , H04N7/26 , H04N7/50 , H04N21/2381 , H04N21/438 , H04N21/61 , H04N21/643 , H04N21/647 , H04Q11/04 , H04N7/04
CPC分类号： H04Q11/0478 , G06F13/128 , H04L12/2602 , H04L12/5602 , H04L43/00 , H04L45/745 , H04L47/10 , H04L47/11 , H04L47/263 , H04L49/3081 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L49/9094 , H04N19/00 , H04N19/42 , H04N19/61 , H04N21/2381 , H04N21/4381 , H04N21/6137 , H04N21/64307 , H04N21/6473 , H04N21/64738 , H04N21/64792 , H04L2012/5613 , H04L2012/5614 , H04L2012/5615 , H04L2012/5616 , H04L2012/5628 , H04L2012/5632 , H04L2012/5635 , H04L2012/5636 , H04L2012/5637 , H04L2012/5638 , H04L2012/5647 , H04L2012/5652 , H04L2012/5653 , H04L2012/5664 , H04L2012/5665 , H04L43/0817 , H04L43/0852 , H04L43/0894 , H04L43/10 , H04L43/106 , H04L49/20 , H04L49/30 , H04L49/3009 , H04N19/70 , H04Q2213/13034 , H04Q2213/13097 , H04Q2213/13141 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/13216 , H04Q2213/13296 , H04Q2213/13322 , H04Q2213/13332 , H04Q2213/13353 , Y02B60/31
摘要： A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets. The interconnection further includes a Virtual Channel Memory (VCM) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for connecting the VCR to the compression/decompression circuits, a Parallel Cell Interface (PCI) for connecting the VCM to an ATM network, a Pacing Rate Unit (PCU) for automatically reducing the maximum transmission rate in response to a sensed congestion condition in the network, and a Reduced Instruction Set Computer (RISC) microprocessor for controlling the DMA controller and transfers between the memory, a host and the ATM network, for performing segmentation and reassembly of Conversion Sublayer Payload Data Units (CD-PDUs), and for performing conversion between the ATM Protocol and the MPEG protocol. The compression/decompression and decoder/encoder circuits may utilize MPEG to compress digitized images and motion video into compact data streams that can be moved across networks with bandwidths too narrow to accommodate the uncompressed data. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which can be downloaded at initialization.
摘要翻译：高速数字视频网络设备在单个集成电路芯片上实现，包括网络协议处理系统互连，压缩/解压缩电路和编码器/解码器电路。互连包括在诸如异步传输模式（ATM）分组之类的网络协议和用于处理大数据流的数据协议（诸如运动图像专家组（MPEG）分组）之间进行转换的分组转换逻辑。互连还包括用于存储用于分段和重组的ATM信元的虚拟信道存储器（VCM），用于将VCR连接到压缩/解压缩电路的直接存储器访问（DMA）控制器，用于连接VCM的并行单元接口 ATM网络，响应于网络中感测到的拥塞状况而自动降低最大传输速率的起搏速率单元（PCU）以及用于控制DMA控制器并在存储器之间传送的简化指令集计算机（RISC）微处理器，主机和ATM网络，用于执行转换子层有效载荷数据单元（CD-PDU）的分段和重组，并且用于在ATM协议和MPEG协议之间执行转换。压缩/解压缩和解码器/编码器电路可以利用MPEG将数字化图像和运动视频压缩成紧密数据流，其可以跨越具有太窄的带宽的网络移动以适应未压缩的数据。 RISC微处理器的操作程序以固件的形式存储在易失性指令随机存取存储器（IRAM）中，可以在初始化时下载。

3. 发明授权

US6026088A Network architecture 失效
标题翻译：网络架构
公开(公告)号：US6026088A
公开(公告)日：2000-02-15
申请号：US412536
申请日：1995-03-28
申请人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
发明人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
IPC分类号： G06F13/12 , H04L12/26 , H04L12/403 , H04L12/56 , H04N7/26 , H04N7/50 , H04N21/2381 , H04N21/4143 , H04N21/437 , H04N21/438 , H04N21/4385 , H04N21/4788 , H04N21/64 , H04N21/643 , H04Q11/04 , H04L12/40
CPC分类号： H04L49/9063 , G06F13/128 , H04L12/40032 , H04L12/5601 , H04L45/745 , H04L49/109 , H04L49/206 , H04L49/25 , H04L49/3081 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L49/9078 , H04L49/9094 , H04N19/00 , H04N19/42 , H04N19/61 , H04N21/2381 , H04N21/4143 , H04N21/437 , H04N21/4381 , H04N21/4385 , H04N21/4788 , H04N21/64 , H04N21/64307 , H04Q11/0478 , H04L2012/5613 , H04L2012/5616 , H04L2012/5635 , H04L2012/5638 , H04L2012/5653 , H04L2012/5664 , H04L2012/5681 , H04N19/70
摘要： A digital network system accommodates a plurality of network protocols. The digital network system includes a backbone bus for communicating digital information. A first switching interface unit is coupled to the backbone bus and has at least one port connected to a first network. A second switching interface unit is also coupled to the backbone bus and has at least one port connected to a second network. The first and second interface units transferring digital information in first and second network protocols, respectively. First and second memories are coupled to the backbone bus and to the first and second switching interface units, respectively, and store digital information to be transferred between the switching interface units via the backbone bus. The first switching interface unit and the first memory are formed on a single substrate, and the second switching interface unit and the second memory are formed on a single substrate. A controller is coupled to the backbone bus and controls the transfer of digital information from the first switching interface unit to the second switching interface unit.
摘要翻译：数字网络系统容纳多个网络协议。数字网络系统包括用于传送数字信息的骨干总线。第一交换接口单元耦合到主干总线并且具有连接到第一网络的至少一个端口。第二交换接口单元还耦合到主干总线并且具有连接到第二网络的至少一个端口。第一和第二接口单元分别在第一和第二网络协议中传送数字信息。第一和第二存储器分别耦合到主干总线和第一和第二切换接口单元，并且经由主干总线存储要在交换接口单元之间传送的数字信息。第一开关接口单元和第一存储器形成在单个基板上，第二开关接口单元和第二存储器形成在单个基板上。控制器耦合到骨干总线，并控制数字信息从第一切换接口单元传送到第二交换接口单元。

4. 发明授权

US6016401A High speed network interface having SAR plus physical interface 失效
标题翻译：具有SAR加物理接口的高速网络接口
公开(公告)号：US6016401A
公开(公告)日：2000-01-18
申请号：US934684
申请日：1997-09-22
申请人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
发明人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
IPC分类号： G06F13/12 , G06F13/38 , G06F15/17 , H04L12/26 , H04L12/56 , H04N7/50
CPC分类号： H04L49/9063 , G06F13/128 , H04L45/745 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L49/9073 , H04L49/9078 , H04N19/61 , H04L2012/5616 , H04L2012/5638 , H04L2012/5653
摘要： A single chip network interface apparatus includes a host interface circuit for communication with a host system bus, a network interface circuit for interfacing with a network bus, a dual port RAM coupled to the host interface circuit and also coupled to the network interface circuit, and a processor coupled to the dual port ram for converting packets of information between network protocol format and a format suitable for the host system bus.
摘要翻译：单芯片网络接口装置包括用于与主机系统总线通信的主机接口电路，用于与网络总线接口的网络接口电路，耦合到主机接口电路并且还耦合到网络接口电路的双端口RAM，以及耦合到双端口RAM的处理器，用于在网络协议格式和适合于主机系统总线的格式之间转换信息分组。

5. 发明授权

US5872784A High speed single chip digital video network apparatus 失效
标题翻译：高速单片机数字视频网络设备
公开(公告)号：US5872784A
公开(公告)日：1999-02-16
申请号：US412862
申请日：1995-03-28
申请人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
发明人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
IPC分类号： G06F13/12 , G10L19/00 , H04L12/26 , H04L12/56 , H04N7/26 , H04N7/50 , H04N21/2381 , H04N21/4143 , H04N21/437 , H04N21/438 , H04N21/4788 , H04N21/643 , H04Q11/04 , H04N7/04
CPC分类号： H04Q11/0478 , G06F13/128 , H04L12/5602 , H04L45/745 , H04L49/3081 , H04L49/355 , H04L49/90 , H04L49/901 , H04L49/9063 , H04L49/9078 , H04N19/00 , H04N19/154 , H04N19/42 , H04N19/46 , H04N19/61 , H04N19/89 , H04N21/2381 , H04N21/4143 , H04N21/437 , H04N21/4381 , H04N21/4788 , H04N21/64307 , G10L19/00 , H04L2012/5613 , H04L2012/5614 , H04L2012/5616 , H04L2012/5632 , H04L2012/5635 , H04L2012/5636 , H04L2012/5637 , H04L2012/5638 , H04L2012/5652 , H04L2012/5653 , H04L2012/5664 , H04L49/25 , H04L49/30 , H04L49/505 , H04N19/70 , H04Q2213/13034 , H04Q2213/13097 , H04Q2213/13141 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/13216 , H04Q2213/13296 , H04Q2213/13322 , H04Q2213/13332 , H04Q2213/13353
摘要： A remote connection digital processing device with network capability includes on a single chip asynchronous transfer mode (ATM) network protocol processing system interconnection circuits and Motion Picture Experts Group (MPEG) decoder circuits. The ATM interconnection circuits include a physical-layer medium dependent (PMD) unit connected to an ATM network. A transmission convergence (TC)/Framer unit is connected to the PMD unit. An ATM segmentation and reassembly (SAR) unit is connected to the PMD unit. Packet conversion logic is coupled to the ATM SAR unit for converting ATM packets to MPEG format. The MPEG decompression decoder circuits include a demodulator decryption unit coupled to the packet conversion logic. A video decoder is coupled to the demodulator decryption unit. An audio decoder is coupled to the demodulator decryption circuit. A display is coupled to the video decoder. Audio output devices are coupled to the audio decoder.
摘要翻译：具有网络能力的远程连接数字处理设备包括单芯片异步传输模式（ATM）网络协议处理系统互连电路和运动图像专家组（MPEG）解码器电路。 ATM互连电路包括连接到ATM网络的物理层介质依赖（PMD）单元。传输收敛（TC）/成帧器单元连接到PMD单元。 ATM分段和重组（SAR）单元连接到PMD单元。分组转换逻辑耦合到ATM SAR单元，用于将ATM分组转换为MPEG格式。 MPEG解压缩解码器电路包括耦合到分组转换逻辑的解调器解密单元。视频解码器耦合到解调器解密单元。音频解码器耦合到解调器解密电路。显示器耦合到视频解码器。音频输出设备耦合到音频解码器。

6. 发明授权

US5864554A Multi-port network adapter 失效
标题翻译：多端口网络适配器
公开(公告)号：US5864554A
公开(公告)日：1999-01-26
申请号：US412537
申请日：1995-03-28
申请人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
发明人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
IPC分类号： G06F13/12 , H04L12/26 , H04L12/403 , H04L12/56 , H04N5/00 , H04N7/24 , H04N7/26 , H04N7/50 , H04Q11/04
CPC分类号： G06F13/128 , H04L12/2602 , H04L12/40032 , H04L12/5601 , H04L12/5602 , H04L43/00 , H04L45/745 , H04L47/10 , H04L47/11 , H04L47/263 , H04L49/109 , H04L49/206 , H04L49/25 , H04L49/3081 , H04L49/355 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L49/9063 , H04L49/9078 , H04L49/9094 , H04N19/00 , H04N19/42 , H04N19/61 , H04N21/2381 , H04N21/4143 , H04N21/4305 , H04N21/437 , H04N21/4381 , H04N21/4385 , H04N21/4788 , H04N21/64 , H04N21/64307 , H04Q11/0478 , H04L2012/5613 , H04L2012/5614 , H04L2012/5616 , H04L2012/5628 , H04L2012/5632 , H04L2012/5635 , H04L2012/5636 , H04L2012/5637 , H04L2012/5638 , H04L2012/5647 , H04L2012/5652 , H04L2012/5653 , H04L2012/5664 , H04L2012/5681 , H04L43/0817 , H04L43/0852 , H04L43/10 , H04L43/106 , H04L49/20 , H04L49/30 , H04L49/3009 , H04L49/505 , H04N19/70 , H04Q2213/13034 , H04Q2213/13097 , H04Q2213/13141 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/13216 , H04Q2213/13296 , H04Q2213/13322 , H04Q2213/13332 , H04Q2213/13353
摘要： The port in a packet network switching system that a packet should be associated with is determined by retrieving packet address information for a packet that is to be transmitted. A predetermined number of bits from the packet address information is selected to use a hash key, which is used to compute a table address. The contents of the table at that address are compared with the packet address information. If it matches, the packet is transmitted over the port associated with that particular destination address. If it does not match, the table address is incremented by one, and the contents of the new table location identified by the incremented address are compared with the packet address information. A high speed digital video network apparatus which utilizes the hashing function is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits.
摘要翻译：通过检索要发送的分组的分组地址信息来确定分组应该关联的分组网络交换系统中的端口。选择来自分组地址信息的预定数量的比特以使用用于计算表地址的哈希密钥。将该地址表中的内容与数据包地址信息进行比较。如果匹配，则通过与该特定目的地址相关联的端口发送分组。如果不匹配，则表地址增加1，并将由递增地址标识的新表位置的内容与分组地址信息进行比较。利用散列功能的高速数字视频网络设备在单个集成电路芯片上实现，并且包括网络协议处理系统互连，压缩/解压缩电路和编码器/解码器电路。

7. 发明授权

US5887187A Single chip network adapter apparatus 失效
标题翻译：单芯片网络适配器装置
公开(公告)号：US5887187A
公开(公告)日：1999-03-23
申请号：US839464
申请日：1997-04-14
申请人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
发明人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
IPC分类号： G06F13/12 , G06F13/38 , G06F15/17 , H04L12/26 , H04L12/56 , H04N7/50
CPC分类号： H04L49/9063 , G06F13/128 , H04L45/745 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L49/9073 , H04L49/9078 , H04N19/61 , H04L2012/5616 , H04L2012/5638 , H04L2012/5653
摘要： A single chip network adapter apparatus has each component disposed on a single semiconductor chip. The network adapter includes a host interface circuit which is adapted for connection directly to a host system bus. The host interface circuit sends information to and receives information form the host system bus, and has random access memory coupled thereto. A processor is coupled to the random access memory and formats information received from the host system bus to a network protocol format. The processor also converts information received in a network protocol format to a form suitable for the host system bus. A network interface circuit is coupled to the random access memory and is adapted for connection directly to a network. The network interface circuit sends information formatted by the processor to the network and receives information to be converted by the processor from the network.
摘要翻译：单芯片网络适配器装置具有设置在单个半导体芯片上的每个部件。网络适配器包括适于直接连接到主机系统总线的主机接口电路。主机接口电路向主机系统总线发送信息并从主机系统总线接收信息，并具有耦合到其的随机存取存储器。处理器耦合到随机存取存储器并将从主机系统总线接收的信息格式化为网络协议格式。处理器还将以网络协议格式接收的信息转换为适合于主机系统总线的形式。网络接口电路耦合到随机存取存储器，并适于直接连接到网络。网络接口电路将由处理器格式化的信息发送到网络，并接收由处理器从网络转换的信息。

8. 发明授权

US5914955A Switched network hub on a chip 失效
标题翻译：交换网络集线器在芯片上
公开(公告)号：US5914955A
公开(公告)日：1999-06-22
申请号：US412861
申请日：1995-03-28
申请人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
发明人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
IPC分类号： G06F13/12 , H04L12/26 , H04L12/403 , H04L12/56 , H04N5/00 , H04N7/24 , H04N7/26 , H04N7/50 , H04Q11/04 , H04L12/40
CPC分类号： G06F13/128 , H04L12/2602 , H04L12/40032 , H04L12/5601 , H04L12/5602 , H04L43/00 , H04L45/745 , H04L47/10 , H04L47/11 , H04L47/263 , H04L49/109 , H04L49/206 , H04L49/25 , H04L49/3081 , H04L49/355 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L49/9063 , H04L49/9078 , H04L49/9094 , H04N19/00 , H04N19/42 , H04N19/61 , H04N21/2381 , H04N21/4143 , H04N21/4305 , H04N21/437 , H04N21/4381 , H04N21/4385 , H04N21/4788 , H04N21/64 , H04N21/64307 , H04Q11/0478 , H04L2012/5613 , H04L2012/5614 , H04L2012/5616 , H04L2012/5628 , H04L2012/5632 , H04L2012/5635 , H04L2012/5636 , H04L2012/5637 , H04L2012/5638 , H04L2012/5647 , H04L2012/5652 , H04L2012/5653 , H04L2012/5664 , H04L2012/5681 , H04L43/0817 , H04L43/0852 , H04L43/10 , H04L43/106 , H04L49/20 , H04L49/30 , H04L49/3009 , H04L49/505 , H04N19/70 , H04Q2213/13034 , H04Q2213/13097 , H04Q2213/13141 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/13216 , H04Q2213/13296 , H04Q2213/13322 , H04Q2213/13332 , H04Q2213/13353
摘要： A network adapter formed on a single semiconductor substrate. The network adapter includes a host bus interface circuit adapted to be connected to a host data bus. A buffer memory is connected to the host bus interface circuit and temporarily stores digital information received from the host data bus. The digital information received from the host data bus are reformatted into packets according to a network protocol by a reformatting circuits. A processor and a network interface circuit are connected to the reformatting circuits. The processor controls the reformatting of the digital information. The network interface circuit is adapted to be connected to a digital network employing the network protocol.
摘要翻译：形成在单个半导体衬底上的网络适配器。网络适配器包括适于连接到主机数据总线的主机总线接口电路。缓冲存储器连接到主机总线接口电路，并临时存储从主机数据总线接收的数字信息。从主机数据总线接收的数字信息通过重新格式化电路根据网络协议重新格式化为数据包。处理器和网络接口电路连接到重新格式化电路。处理器控制数字信息的重新格式化。网络接口电路适于使用网络协议连接到数字网络。

9. 发明授权

US06754196B1 Method and apparatus for increasing the effective bandwidth within a digital wireless network 失效
标题翻译：用于增加数字无线网络内的有效带宽的方法和装置
公开(公告)号：US06754196B1
公开(公告)日：2004-06-22
申请号：US09063476
申请日：1998-04-20
申请人： John Daane , Michael D. Rostoker , Sandeep Jaggi
发明人： John Daane , Michael D. Rostoker , Sandeep Jaggi
IPC分类号： H04Q724
CPC分类号： H04W72/0453
摘要： A plurality of devices communicate information over a wireless network at radio frequencies. The information includes digital audio, video and data. Bandwidth among the devices is dynamically allocated, the allocation being based upon the needs of the devices. One embodiment of the wireless network is a Time Division Multiple Access network. Another embodiment is a wireless Ethernet. Yet another embodiment is a Frequency Division Multiplexed network.
摘要翻译：多个设备通过无线电频率的无线网络传送信息。信息包括数字音频，视频和数据。动态分配设备之间的带宽，根据设备的需要进行分配。无线网络的一个实施例是时分多址网络。另一个实施例是无线以太网。另一个实施例是频分复用网络。

10. 发明授权

US06418353B1 Automating photolithography in the fabrication of integrated circuits 失效
标题翻译：在制造集成电路时自动化光刻
公开(公告)号：US06418353B1
公开(公告)日：2002-07-09
申请号：US09064802
申请日：1998-04-22
申请人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
发明人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
IPC分类号： G06F1900
CPC分类号： G03F7/705 , G03F7/70433 , G03F7/70625
摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and. yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.
摘要翻译：集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。制造数据包括流程和。然后将产量参数转移回瑞利处理器用于后续电路的设计。以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

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