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1. 发明申请

US20120317527A1 PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION 失效
标题翻译：硬件加速功能验证分区
公开(公告)号：US20120317527A1
公开(公告)日：2012-12-13
申请号：US13590115
申请日：2012-08-20
申请人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
发明人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
摘要翻译：使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。松弛可以计算为边缘来源的早期和晚期等级之间的差异。重量可以进一步计算为边缘的松弛和最大松弛值之间的差。在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。边缘和顶点权重可以重新计算下一级分区。分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。

2. 发明授权

US08555221B2 Partitioning for hardware-accelerated functional verification 失效
标题翻译：分区硬件加速功能验证
公开(公告)号：US08555221B2
公开(公告)日：2013-10-08
申请号：US13590115
申请日：2012-08-20
申请人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
发明人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
摘要翻译：使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。松弛可以计算为边缘来源的早期和晚期等级之间的差异。重量可以进一步计算为边缘的松弛和最大松弛值之间的差。在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。边缘和顶点权重可以重新计算下一级分区。分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。

3. 发明授权

US08327304B2 Partitioning for hardware-accelerated functional verification 有权
标题翻译：分区硬件加速功能验证
公开(公告)号：US08327304B2
公开(公告)日：2012-12-04
申请号：US12949328
申请日：2010-11-18
申请人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
发明人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
摘要翻译：使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。松弛可以计算为边缘来源的早期和晚期等级之间的差异。重量可以进一步计算为边缘的松弛和最大松弛值之间的差。在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。边缘和顶点权重可以重新计算下一级分区。分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。

4. 发明申请

US20120131530A1 PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION 有权
公开(公告)号：US20120131530A1
公开(公告)日：2012-05-24
申请号：US12949328
申请日：2010-11-18
申请人： MICHAEL D. MOFFITT , Matyas A. Sustik , Paul G. Villarrubia
发明人： MICHAEL D. MOFFITT , Matyas A. Sustik , Paul G. Villarrubia
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

5. 发明授权

US09524363B2 Element placement in circuit design based on preferred location 有权
标题翻译：基于优选位置的电路设计元素放置
公开(公告)号：US09524363B2
公开(公告)日：2016-12-20
申请号：US13485828
申请日：2012-05-31
申请人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5081
摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
摘要翻译：改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

6. 发明授权

US06671867B2 Analytical constraint generation for cut-based global placement 有权
公开(公告)号：US06671867B2
公开(公告)日：2003-12-30
申请号：US10121877
申请日：2002-04-11
申请人： Charles J. Alpert , Gi-Joon Nam , Paul G. Villarrubia
发明人： Charles J. Alpert , Gi-Joon Nam , Paul G. Villarrubia
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： A method of designing the layout of an integrated circuit (IC) by deriving an analytical constraint for a cut-based placement partitioner using analytical optimization, and placing cells on the IC with the cut-based placement partitioner using the analytical constraint. Quadratic optimization may be used to determine a desired ratio of a cell area of a given partition to a total cell area (the balance parameter), and placing may be performed using multilevel bisection partitioning constrained by the balance parameter. This implementation may include a determination of an aspect ratio for an entire partitioning region of the integrated circuit, and a “center-of-mass” coordinate of the cells based on the quadratic optimization, which are then used to define a placement rectangle having the same aspect ratio, and centered on the center-of-mass coordinate. This placement rectangle is used to derive the balance parameter. The placement rectangle has a total area equal to a total moveable cell area, and the balance parameter is computed by calculating the ratio of a left portion of the placement rectangle which lies in the left partition to the total area of the placement rectangle. The multilevel partitioner then places a proportionate number of the cells in the left partition based on the balance parameter.

7. 发明申请

US20120284733A1 Scheduling for Parallel Processing of Regionally-Constrained Placement Problem 有权
标题翻译：并行处理区域约束布局的调度问题
公开(公告)号：US20120284733A1
公开(公告)日：2012-11-08
申请号：US13550957
申请日：2012-07-17
申请人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
发明人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
IPC分类号： G06F9/46
CPC分类号： G06F17/50 , G06F9/5066
摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.
摘要翻译：区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。对于少量的移动端口，通过平衡可放置对象来分配计算。对于每次移动的少量对象，通过平衡移动端口分配计算。如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。对于对象平衡，移动端口被分配给一个处理器，直到处理器的摊销对象数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。本发明提供多项式时间的时间表，同时保持高质量的结果。

8. 发明授权

US07467369B2 Constrained detailed placement 有权
标题翻译：约束详细的布置
公开(公告)号：US07467369B2
公开(公告)日：2008-12-16
申请号：US11554235
申请日：2006-10-30
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072
摘要： The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.
摘要翻译：说明性实施例提供了一种计算机实现的方法，其执行减小总线长度的小区变换，而不降低设备定时或违反电气约束。该过程计算数据集的延迟约束系数。该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。该过程计算用于变换数据集合的加权总线长度递增值。此外，该过程通过评估抵达时间约束，电气约束和用户可配置的违规移动限制，以及如果发现违规，则将移动单元恢复到原始位置继续。

9. 发明申请

US20080282213A1 METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 有权
标题翻译：通过扩展力矢量调制降低分析放置技术的线性的方法
公开(公告)号：US20080282213A1
公开(公告)日：2008-11-13
申请号：US12181447
申请日：2008-07-29
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

10. 发明申请

US20080209376A1 SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP 失效
标题翻译： VLSI芯片的关闭时序关闭的系统和方法
公开(公告)号：US20080209376A1
公开(公告)日：2008-08-28
申请号：US11680110
申请日：2007-02-28
申请人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.
摘要翻译：一种用于以紧密耦合的递增方式对细节路由网表执行定时优化的方法，其以最小的扰动对放置，路由和断言的寄生信息进行并入，并入统计变异信息，公共路径悲观度降低和电容耦合信息。该方法校正了VLSI电路芯片的放置和路由设计中的违规，其中设计由描述设计的逻辑和物理特性的网表以及对应的时序图表示，该方法包括以下步骤：识别设计; 通过逐步改变设计的逻辑和物理特征，迭代地消除违规行为，仅在设计中纳入合法的布局和路线; 并应用增量时间来评估变革，并更新现有的时间图，以反映由法定刊登位置和路线组成的变更。

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