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1. 发明授权

US07002874B1 Dual word line mode for DRAMs 有权
标题翻译： DRAM的双字线模式
公开(公告)号：US07002874B1
公开(公告)日：2006-02-21
申请号：US11081191
申请日：2005-03-16
申请人： Michael C. Parris , Douglas Blaine Butler , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Douglas Blaine Butler , Oscar Frederick Jones, Jr.
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.
摘要翻译：集成电路存储器包括用于在每个位操作模式下单独激活第一个存储单元中的字线的电路，同时在第二操作模式中激活至少两个字线，其中两个或多个存储器单元专用于每个数据位，并提供一个当将存储单元阵列中的存储数据从第一操作模式转换为第二操作模式时，字线序列。字线序列包括激活第一字线，在对应位线上形成有效信号，然后在第一字线仍然有效时激活第二字线。

2. 发明申请

US20090106488A1 STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKS 审中-公开
标题翻译：静态随机访问存储器（SRAM）兼容，高可用性存储器阵列和方法使用与数据缓存连续的同步动态随机访问存储器（DRAM）和分离读取和写入寄存器和标签块
公开(公告)号：US20090106488A1
公开(公告)日：2009-04-23
申请号：US12254702
申请日：2008-10-20
申请人： Douglas Blaine Butler , Oscar Frederick Jones, JR. , Michael C. Parris , Kim C. Hardee
发明人： Douglas Blaine Butler , Oscar Frederick Jones, JR. , Michael C. Parris , Kim C. Hardee
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G11C11/406 , G11C11/40607 , G11C11/4076
摘要： A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.
摘要翻译：高速，静态随机存取存储器（SRAM）兼容，高可用性存储器阵列和采用同步动态随机存取存储器（DRAM）结合数据高速缓存和单独的数据读写寄存器和标签块的方法。包含单独的数据读写寄存器允许器件在仅由DRAM子阵列周期时间限制的周期时间内有效地工作。此外，包含两个标签块允许用外部提供的地址访问一个，另一个使用回写地址进行访问，因此消除了对单个标签在一个DRAM中执行两个读取 - 修改写入周期的要求周期。

3. 发明授权

US07110306B2 Dual access DRAM 有权
标题翻译：双通道DRAM
公开(公告)号：US07110306B2
公开(公告)日：2006-09-19
申请号：US10878800
申请日：2004-06-28
申请人： Michael C. Parris , Oscar Frederick Jones, Jr. , Douglas Blaine Butler
发明人： Michael C. Parris , Oscar Frederick Jones, Jr. , Douglas Blaine Butler
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C7/1075 , G11C11/4093 , G11C2207/002
摘要： A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.
摘要翻译：双存取DRAM包括第一和第二组数据线。通过将第二组复用晶体管添加到与现有的多路复用晶体管类似的定时和寻址控制的数据线上，可以通过额外的一组数据线将数据传输到第二子阵列。第二组数据线是除了正常的数据线之外使用的附加内部读/写线。第二组数据线被设计为具有相应低电容的短长度，使得读出放大器上的额外负载较小。

4. 发明授权

US07099234B2 Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM 有权
标题翻译：用于动态随机存取存储器（DRAM）器件和集成嵌入式DRAM的集成电路器件的低功耗睡眠模式操作技术
公开(公告)号：US07099234B2
公开(公告)日：2006-08-29
申请号：US10878925
申请日：2004-06-28
申请人： Michael C. Parris , Oscar Frederick Jones, Jr. , Douglas Blaine Butler
发明人： Michael C. Parris , Oscar Frederick Jones, Jr. , Douglas Blaine Butler
IPC分类号： G11C8/00
CPC分类号： G11C11/406 , G11C5/144 , G11C11/40626 , G11C2211/4067 , G11C2211/4068
摘要： A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary with all possible process corners, voltages and temperatures (PVT) since the clock signal exhibits a steady frequency over PVT applied to the DRAM and an internal timer placed on chip will vary directly with these parameters. After entering Sleep Mode, the main internal clock signal is inhibited from propagating around the device chip and, at this time, much of the associated circuitry can be power-gated to conserve power, typically with signals that have a boosted level to provide a negative gate-to-source voltage (VGS) on the power-gating transistors.
摘要翻译：一种用于动态随机存取（DRAM）器件和集成嵌入式DRAM的集成电路器件的低功耗睡眠模式操作技术。通过根据所公开的技术对时钟（CLK）周期进行计数，由于时钟信号表现出稳定的频率，因此所有可能的处理角，电压和温度（PVT）都不会改变刷新时间（t REF REF）通过施加到DRAM的PVT和放置在芯片上的内部定时器将随着这些参数而变化。在进入睡眠模式之后，禁止主内部时钟信号在器件芯片周围传播，此时，大部分相关电路可以通过电源门控来节省功耗，通常使用具有提升电平的信号来提供负极电源门控晶体管上的栅极至源极电压（V SUB）。

5. 发明授权

US06912168B2 Non-contiguous masked refresh for an integrated circuit memory 有权
标题翻译：集成电路存储器的非连续屏蔽刷新
公开(公告)号：US06912168B2
公开(公告)日：2005-06-28
申请号：US10391315
申请日：2003-03-18
申请人： Michael C. Parris , Douglas Blaine Butler , Kim C. Hardee , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Douglas Blaine Butler , Kim C. Hardee , Oscar Frederick Jones, Jr.
IPC分类号： G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40611 , G11C11/40622
摘要： A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which should be not refreshed. Power is saved due to the flexibility in determining which subarrays are refreshed at each new refresh cycle.
摘要翻译：刷新电路用于从集成电路存储器阵列中的刷新非连续子阵列刷新或屏蔽。在每个被屏蔽的刷新周期的开始，通常被忽略的地址输入被评估，以指示哪些子阵列应被刷新，哪些不应该被刷新。由于可以灵活地确定在每个新的刷新周期刷新哪些子阵列，所以节省了电力。

6. 发明授权

US07506100B2 Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks 有权
标题翻译：静态随机存取存储器（SRAM）兼容，高可用性存储器阵列和采用同步动态随机存取存储器（DRAM）结合数据高速缓存和单独读写寄存器和标签块的方法
公开(公告)号：US07506100B2
公开(公告)日：2009-03-17
申请号：US11064354
申请日：2005-02-23
申请人： Douglas Blaine Butler , Oscar Frederick Jones, Jr. , Michael C. Parris , Kim C. Hardee
发明人： Douglas Blaine Butler , Oscar Frederick Jones, Jr. , Michael C. Parris , Kim C. Hardee
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G11C11/406 , G11C11/40607 , G11C11/4076
摘要： A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.
摘要翻译：高速，静态随机存取存储器（SRAM）兼容，高可用性存储器阵列和采用同步动态随机存取存储器（DRAM）结合数据高速缓存和单独的数据读写寄存器和标签块的方法。包含单独的数据读写寄存器允许器件在仅由DRAM子阵列周期时间限制的周期时间内有效地工作。此外，包含两个标签块允许用外部提供的地址访问一个，另一个使用回写地址进行访问，因此消除了对单个标签在一个DRAM中执行两个读取 - 修改写入周期的要求周期。

7. 发明授权

US06608797B1 Automatic delay technique for early read and write operations in synchronous dynamic random access memories 有权
标题翻译：自动延迟技术用于同步动态随机存取存储器中的早期读写操作
公开(公告)号：US06608797B1
公开(公告)日：2003-08-19
申请号：US10125756
申请日：2002-04-18
申请人： Michael C. Parris , Kim C. Hardee , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Kim C. Hardee , Oscar Frederick Jones, Jr.
IPC分类号： G11C800
CPC分类号： G11C11/4087 , G11C7/1048 , G11C7/1072 , G11C2207/002 , G11C2207/2281 , G11C2207/229
摘要： An automatic delay technique for early “read” and “write” memory access operations in synchronous dynamic random access memory (“SDRAM”) devices and those integrated circuit devices employing embedded SDRAM arrays. A circuit and method is provided which controls the internal column select (“Yi”) and data signals such that the column address strobe (“/CAS”) signal is allowed to go “active” in advance of that otherwise possible in conjunction with conventional SDRAM arrays. In an exemplary embodiment, the column select signals (“read” or “write”) are delayed until either the corresponding, pre-decoded column address signal or the respective column clock signal is valid, whichever occurs later.
摘要翻译：一种用于同步动态随机存取存储器（“SDRAM”）器件和采用嵌入式SDRAM阵列的那些集成电路器件的早期“读取”和“写入”存储器访问操作的自动延迟技术。提供了一种电路和方法，其控制内部列选择（“Yi”）和数据信号，使得列地址选通（“/ CAS”）信号被允许进行“活动”，否则可能结合常规 SDRAM阵列。在示例性实施例中，列选择信号（“读”或“写”）被延迟，直到相应的预解码列地址信号或相应的列时钟信号有效为止，以较晚者为准。

8. 发明申请

US20090094497A1 DATA INVERSION REGISTER TECHNIQUE FOR INTEGRATED CIRCUIT MEMORY TESTING 有权
标题翻译：用于集成电路存储器测试的数据反相寄存器技术
公开(公告)号：US20090094497A1
公开(公告)日：2009-04-09
申请号：US11868509
申请日：2007-10-07
申请人： Michael C. Parris , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Oscar Frederick Jones, Jr.
IPC分类号： G01R31/28
CPC分类号： G01R31/31713 , G11C29/10 , G11C29/56 , G11C2029/0409
摘要： A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.
摘要翻译：一种用于集成电路存储器测试的数据反转寄存器技术，其中数据输入信号以预定模式选择性地反转，以最大化在测试期间识别故障的可能性。根据本发明的技术，在预定的输入/输出（I / O））数据输入可以被反转以创建对于I / O电路是“最坏情况”的期望的测试图案（诸如数据条纹），或者列条纹是存储器阵列的“最坏情况”。根据本发明的技术的电路然后匹配数据输出路径的模式，反转适当的数据输出以获得预期的测试器数据。这样，测试模式对任何记忆测试仪都是透明的。

9. 发明申请

US20090015311A1 LOW SKEW CLOCK DISTRIBUTION TREE 有权
标题翻译：低穗时钟分配树
公开(公告)号：US20090015311A1
公开(公告)日：2009-01-15
申请号：US11776371
申请日：2007-07-11
申请人： Michael C. Parris , Oscar Frederick Jones, JR.
发明人： Michael C. Parris , Oscar Frederick Jones, JR.
IPC分类号： H03K3/84
CPC分类号： G06F1/10 , G11C5/063 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093
摘要： A clock distribution tree for an integrated circuit memory includes a set of data drivers, a corresponding set of input buffers coupled to the data drivers, a first clock distribution tree coupled to the data drivers, and a second clock distribution tree coupled to the input buffers, wherein the first and second clock distribution tree are substantially matched and mirrored distribution trees. The line width of the first clock distribution tree is substantially the same as the line width of the second clock distribution tree. The line spacing of the first clock distribution tree is substantially the same as the line spacing of the second clock distribution tree. Numerous topologies for the first and second clock distribution trees can be accommodated, as long as they are matched and mirrored. Valid times for the integrated circuit memory are maximized and data and clock skew is minimized.
摘要翻译：用于集成电路存储器的时钟分配树包括一组数据驱动器，耦合到数据驱动器的相应的输入缓冲器组，耦合到数据驱动器的第一时钟分配树，以及耦合到输入缓冲器的第二时钟分配树，其中所述第一和第二时钟分布树基本匹配并且镜像分布树。第一时钟分配树的线宽基本上与第二时钟分配树的线宽相同。第一时钟分配树的行间距基本上与第二时钟分配树的行间隔相同。只要匹配和镜像，可以容纳第一和第二时钟分配树的许多拓扑。集成电路存储器的有效时间最大化，数据和时钟偏移最小化。

10. 发明授权

US06643212B1 Simultaneous function dynamic random access memory device technique 有权
标题翻译：同步功能动态随机存取存储器件技术
公开(公告)号：US06643212B1
公开(公告)日：2003-11-04
申请号：US10125758
申请日：2002-04-18
申请人： Oscar Frederick Jones, Jr. , Michael C. Parris
发明人： Oscar Frederick Jones, Jr. , Michael C. Parris
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1042 , G11C2207/104 , G11C2207/108 , G11C2207/2281 , G11C2207/229
摘要： A simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like which enables the execution of “read”, “write”, “active” and “precharge” commands on a single clock cycle. The technique of the present invention is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the advantages of the technique are obtained through the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.
摘要翻译：特别适用于DRAM，同步DRAM（“SDRAM”），专用DRAM，嵌入式DRAM，嵌入式SDRAM等的同时功能动态随机存取存储器（“DRAM”）技术，其能够执行“读取”，“写入” ，“活动”和“预充电”命令。本发明的技术特别适用于嵌入式存储器阵列或特殊DRAM，其中DRAM的输入信号的数量不一定受到机械部件封装约束或分量引脚计数的限制。一般来说，该技术的优点是通过使用单独的地址字段（包括用于“读取”和“写入”命令的存储区地址）来获得，并且通过使用高度并行的“高效”命令来分离“活动”和“预充电”命令的存储体地址操作功能。

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