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1. 发明申请

US20090106488A1 STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKS 审中-公开
标题翻译：静态随机访问存储器（SRAM）兼容，高可用性存储器阵列和方法使用与数据缓存连续的同步动态随机访问存储器（DRAM）和分离读取和写入寄存器和标签块
公开(公告)号：US20090106488A1
公开(公告)日：2009-04-23
申请号：US12254702
申请日：2008-10-20
申请人： Douglas Blaine Butler , Oscar Frederick Jones, JR. , Michael C. Parris , Kim C. Hardee
发明人： Douglas Blaine Butler , Oscar Frederick Jones, JR. , Michael C. Parris , Kim C. Hardee
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G11C11/406 , G11C11/40607 , G11C11/4076
摘要： A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.
摘要翻译：高速，静态随机存取存储器（SRAM）兼容，高可用性存储器阵列和采用同步动态随机存取存储器（DRAM）结合数据高速缓存和单独的数据读写寄存器和标签块的方法。包含单独的数据读写寄存器允许器件在仅由DRAM子阵列周期时间限制的周期时间内有效地工作。此外，包含两个标签块允许用外部提供的地址访问一个，另一个使用回写地址进行访问，因此消除了对单个标签在一个DRAM中执行两个读取 - 修改写入周期的要求周期。

2. 发明授权

US07110306B2 Dual access DRAM 有权
标题翻译：双通道DRAM
公开(公告)号：US07110306B2
公开(公告)日：2006-09-19
申请号：US10878800
申请日：2004-06-28
申请人： Michael C. Parris , Oscar Frederick Jones, Jr. , Douglas Blaine Butler
发明人： Michael C. Parris , Oscar Frederick Jones, Jr. , Douglas Blaine Butler
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C7/1075 , G11C11/4093 , G11C2207/002
摘要： A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.
摘要翻译：双存取DRAM包括第一和第二组数据线。通过将第二组复用晶体管添加到与现有的多路复用晶体管类似的定时和寻址控制的数据线上，可以通过额外的一组数据线将数据传输到第二子阵列。第二组数据线是除了正常的数据线之外使用的附加内部读/写线。第二组数据线被设计为具有相应低电容的短长度，使得读出放大器上的额外负载较小。

3. 发明授权

US07099234B2 Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM 有权
标题翻译：用于动态随机存取存储器（DRAM）器件和集成嵌入式DRAM的集成电路器件的低功耗睡眠模式操作技术
公开(公告)号：US07099234B2
公开(公告)日：2006-08-29
申请号：US10878925
申请日：2004-06-28
申请人： Michael C. Parris , Oscar Frederick Jones, Jr. , Douglas Blaine Butler
发明人： Michael C. Parris , Oscar Frederick Jones, Jr. , Douglas Blaine Butler
IPC分类号： G11C8/00
CPC分类号： G11C11/406 , G11C5/144 , G11C11/40626 , G11C2211/4067 , G11C2211/4068
摘要： A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary with all possible process corners, voltages and temperatures (PVT) since the clock signal exhibits a steady frequency over PVT applied to the DRAM and an internal timer placed on chip will vary directly with these parameters. After entering Sleep Mode, the main internal clock signal is inhibited from propagating around the device chip and, at this time, much of the associated circuitry can be power-gated to conserve power, typically with signals that have a boosted level to provide a negative gate-to-source voltage (VGS) on the power-gating transistors.
摘要翻译：一种用于动态随机存取（DRAM）器件和集成嵌入式DRAM的集成电路器件的低功耗睡眠模式操作技术。通过根据所公开的技术对时钟（CLK）周期进行计数，由于时钟信号表现出稳定的频率，因此所有可能的处理角，电压和温度（PVT）都不会改变刷新时间（t REF REF）通过施加到DRAM的PVT和放置在芯片上的内部定时器将随着这些参数而变化。在进入睡眠模式之后，禁止主内部时钟信号在器件芯片周围传播，此时，大部分相关电路可以通过电源门控来节省功耗，通常使用具有提升电平的信号来提供负极电源门控晶体管上的栅极至源极电压（V SUB）。

4. 发明授权

US06912168B2 Non-contiguous masked refresh for an integrated circuit memory 有权
标题翻译：集成电路存储器的非连续屏蔽刷新
公开(公告)号：US06912168B2
公开(公告)日：2005-06-28
申请号：US10391315
申请日：2003-03-18
申请人： Michael C. Parris , Douglas Blaine Butler , Kim C. Hardee , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Douglas Blaine Butler , Kim C. Hardee , Oscar Frederick Jones, Jr.
IPC分类号： G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40611 , G11C11/40622
摘要： A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which should be not refreshed. Power is saved due to the flexibility in determining which subarrays are refreshed at each new refresh cycle.
摘要翻译：刷新电路用于从集成电路存储器阵列中的刷新非连续子阵列刷新或屏蔽。在每个被屏蔽的刷新周期的开始，通常被忽略的地址输入被评估，以指示哪些子阵列应被刷新，哪些不应该被刷新。由于可以灵活地确定在每个新的刷新周期刷新哪些子阵列，所以节省了电力。

5. 发明授权

US06337278B1 Technique for forming a borderless overlapping gate and diffusion contact structure in integrated circuit device processing 有权
标题翻译：在集成电路器件加工中形成无边界重叠栅极和扩散接触结构的技术
公开(公告)号：US06337278B1
公开(公告)日：2002-01-08
申请号：US09644346
申请日：2000-08-23
申请人： Douglas Blaine Butler
发明人： Douglas Blaine Butler
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A technique for forming a borderless transistor gate and source/drain region contact structure which provides an on-chip area efficient layout and connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment, this may be effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion. The structure and process of the present invention provides a desirable size reduction in the contact for given design rule dimensions and the resultant contact structure is inherently “self-aligned” to both the gate polysilicon layer and the isolation region in that the contact has no need for an interstitial space between it and the gate polysilicon or isolation regions to prevent unintended electrical connections.
摘要翻译：一种用于形成无边界晶体管栅极和源极/漏极区接触结构的技术，其提供在器件栅极层与相邻源极/漏极区域之间的片上区域有效布局和连接，其也可以与相邻的隔离结构重叠。在代表性的实施例中，这可以通过栅极多晶硅层的边缘上的接触区域的一部分的重叠和源极/漏极扩散部分上的接触的另一部分重叠来实现。本发明的结构和方法为给定的设计规则尺寸提供了理想的接触尺寸减小，并且所得的接触结构固有地对栅极多晶硅层和隔离区“自对准”，因为接触不再需要用于其与栅极多晶硅或隔离区之间的间隙空间，以防止意外的电连接。

6. 发明申请

US20090225613A1 TWIN CELL ARCHITECTURE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES AND THOSE DEVICES INCORPORATING EMBEDDED DRAM 有权
标题翻译：用于集成电路动态随机存取存储器（DRAM）器件和包含嵌入式DRAM的器件的双细胞结构
公开(公告)号：US20090225613A1
公开(公告)日：2009-09-10
申请号：US12044664
申请日：2008-03-07
申请人： Michael C. Parris , Douglas Blaine Butler
发明人： Michael C. Parris , Douglas Blaine Butler
IPC分类号： G11C7/00 , G11C7/06
CPC分类号： G11C11/404 , G11C7/02 , G11C7/1006 , G11C11/4097 , G11C2211/4013
摘要： A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in terms of power, radiation hardness and speed and does not require intermediate supply voltage bitline precharge while allowing for 6F2 memory cell layouts.
摘要翻译：公开了一种用于动态随机存取存储器（DRAM）器件的双电池架构以及采用开放位线配置的嵌入式DRAM的那些器件。所公开的双电池结构在功率，辐射硬度和速度方面比传统设计具有显着的优点，并且不需要中间电源电压位线预充电，同时允许6F2存储器单元布局。

7. 发明申请

US20080268646A1 REDUCED AREA DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：减少区域动态随机存取存储器（DRAM）单元及其制造方法
公开(公告)号：US20080268646A1
公开(公告)日：2008-10-30
申请号：US12168748
申请日：2008-07-07
申请人： Douglas Blaine Butler , Chia-Shun Hsiao , Jung-Wu Chien , Chih-Hsun Chu
发明人： Douglas Blaine Butler , Chia-Shun Hsiao , Jung-Wu Chien , Chih-Hsun Chu
IPC分类号： H01L21/311
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.
摘要翻译：一种缩小面积动态随机存取存储器（DRAM）单元及其制造方法，其中通过沿着第一图案形成侧壁间隔物，通过两个光刻间距占据小于一个光刻间距的区域，以限定活动的第一部分存储单元的区域和第二正交定向图案，以限定存储单元的有源区域的第二部分，从而为存储单元的列创建梯形有源区域。

8. 发明授权

US06518829B2 Driver timing and circuit technique for a low noise charge pump circuit 有权
标题翻译：低噪声电荷泵电路的驱动时序和电路技术
公开(公告)号：US06518829B2
公开(公告)日：2003-02-11
申请号：US09730207
申请日：2000-12-04
申请人： Douglas Blaine Butler
发明人： Douglas Blaine Butler
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： A driver timing and circuit technique for a low noise charge pump circuit of particular applicability with respect to integrated circuit devices requiring voltage levels either more positive than or more negative than, externally supplied voltages. In accordance with the technique of the present invention, the pump capacitor is driven “high” by one transistor and “low” by another. By correctly sizing the devices driving them, each transistor can be turned “off” quickly and “on” slowly and, in an alternative embodiment, both transistors may be “off” at the same time resulting in “tri-state” operation. Timing is set such that both transistors are “off” when a third transistor connecting the intermediate node to the power supply is turned “on” and when a fourth transistor connecting the intermediate node to the pumped supply is turned “on” thereby preventing large dI/dt and resultant noise on the power supply sources.
摘要翻译：用于低噪声电荷泵电路的驱动器时序和电路技术，其特别适用于需要比外部提供的电压更正或更负的电压电平的集成电路器件。根据本发明的技术，泵电容器由一个晶体管驱动“高”，另一个驱动“低”。通过对驱动它们的器件进行正确的尺寸调整，可以将每个晶体管快速地“关闭”并且“开”，并且在另一实施例中，两个晶体管可能同时“关闭”，导致“三态”操作。当连接中间节点与电源的第三晶体管接通时，并且当将中间节点连接到泵浦电源的第四晶体管“接通”时，两个晶体管都被设置为“截止”，从而防止了大的dI / dt和电源上产生的噪声。

9. 发明授权

US07583110B2 High-speed, low-power input buffer for integrated circuit devices 有权
标题翻译：用于集成电路器件的高速，低功耗输入缓冲器
公开(公告)号：US07583110B2
公开(公告)日：2009-09-01
申请号：US11687605
申请日：2007-03-16
申请人： Douglas Blaine Butler
发明人： Douglas Blaine Butler
IPC分类号： H03B1/00
CPC分类号： G11C7/1078 , G11C7/1084
摘要： A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.
摘要翻译：用于集成电路器件的高速，低功耗输入缓冲器，其中输入电压（VIN）耦合到上拉和下拉晶体管。根据具体实施例，输入缓冲器在操作的校准阶段期间利用参考电压输入（VREF），但在主动操作模式中不使用输入缓冲器。当VIN = VREF时，在所有其他VIN电压下具有较低的通过电流电平时，提供最大电流通过电流。在包含所公开的输入缓冲器的集成电路装置中，每个器件输入引脚可以使用两个（或多个）输入缓冲器。

10. 发明授权

US07506100B2 Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks 有权
标题翻译：静态随机存取存储器（SRAM）兼容，高可用性存储器阵列和采用同步动态随机存取存储器（DRAM）结合数据高速缓存和单独读写寄存器和标签块的方法
公开(公告)号：US07506100B2
公开(公告)日：2009-03-17
申请号：US11064354
申请日：2005-02-23
申请人： Douglas Blaine Butler , Oscar Frederick Jones, Jr. , Michael C. Parris , Kim C. Hardee
发明人： Douglas Blaine Butler , Oscar Frederick Jones, Jr. , Michael C. Parris , Kim C. Hardee
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G11C11/406 , G11C11/40607 , G11C11/4076
摘要： A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.
摘要翻译：高速，静态随机存取存储器（SRAM）兼容，高可用性存储器阵列和采用同步动态随机存取存储器（DRAM）结合数据高速缓存和单独的数据读写寄存器和标签块的方法。包含单独的数据读写寄存器允许器件在仅由DRAM子阵列周期时间限制的周期时间内有效地工作。此外，包含两个标签块允许用外部提供的地址访问一个，另一个使用回写地址进行访问，因此消除了对单个标签在一个DRAM中执行两个读取 - 修改写入周期的要求周期。

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