专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07153761B1 Method of transferring a thin crystalline semiconductor layer 有权
标题翻译：转移薄晶体半导体层的方法
公开(公告)号：US07153761B1
公开(公告)日：2006-12-26
申请号：US11243010
申请日：2005-10-03
申请人： Michael A. Nastasi , Lin Shao , N. David Theodore
发明人： Michael A. Nastasi , Lin Shao , N. David Theodore
IPC分类号： H01L21/322
CPC分类号： H01L21/76254
摘要： A method for transferring a thin semiconductor layer from one substrate to another substrate involves depositing a thin epitaxial monocrystalline semiconductor layer on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the thin semiconductor layer is bonded to a second substrate and the thin layer is separated away at the interface, which results in transferring the thin epitaxial semiconductor layer from one substrate to the other substrate.
摘要翻译：将薄半导体层从一个衬底转移到另一个衬底的方法包括在具有表面污染物的衬底上沉积薄的外延单晶半导体层。在沉积层和基板之间形成包含污染物的界面。氢原子被引入到结构中并允许扩散到界面。之后，薄的半导体层被结合到第二衬底上，并且薄层在界面处被分开，这导致将薄的外延半导体层从一个衬底转移到另一个衬底。

2. 发明授权

US5338932A Method and apparatus for measuring the topography of a semiconductor device 失效
标题翻译：用于测量半导体器件的形貌的方法和装置
公开(公告)号：US5338932A
公开(公告)日：1994-08-16
申请号：US168
申请日：1993-01-04
申请人： N. David Theodore , Juan P. Carrejo
发明人： N. David Theodore , Juan P. Carrejo
IPC分类号： G01Q10/00 , G01Q70/08 , G01Q60/04 , H01J37/00
CPC分类号： G01Q60/04 , B82Y35/00 , Y10S977/851 , Y10S977/854 , Y10S977/861 , Y10S977/873 , Y10S977/874 , Y10S977/953
摘要： The topography of a surface is measured by utilizing a probe (10, 20) having a variable flexibility and a conductive tip (14, 16). Using the conductive tip (14, 16), a first tunneling current is measured at a first point (36). The tip (14, 16) is moved to a second point (37) and a deflection force is measured. The measurements from the different points (36, 37, 38, 39, 40, 41) are combined to provide composite images of the surface's topography and material composition.
摘要翻译：通过利用具有可变柔性的探针（10,20）和导电尖端（14,16）来测量表面的形貌。使用导电尖端（14,16），在第一点（36）处测量第一隧道电流。尖端（14,16）移动到第二点（37），并且测量偏转力。来自不同点（36,37,38,39,40,41）的测量结合以提供表面的地形和材料组成的复合图像。

3. 发明授权

US5565690A Method for doping strained heterojunction semiconductor devices and structure 失效
标题翻译：掺杂应变异质结半导体器件和结构的方法
公开(公告)号：US5565690A
公开(公告)日：1996-10-15
申请号：US382699
申请日：1995-02-02
申请人： N. David Theodore , Donald Y. C. Lie , T. C. Smith , John W. Steele
发明人： N. David Theodore , Donald Y. C. Lie , T. C. Smith , John W. Steele
IPC分类号： H01L21/265 , H01L21/331 , H01L29/167 , H01L29/06
CPC分类号： H01L29/66242 , H01L21/26513 , H01L29/167 , Y10S438/938
摘要： A method for doping a strained heterojunction semiconductor device includes heating a substrate (16) having a strained mono-crystalline semiconductor region (22) to a temperature above room temperature. While the substrate (16) is heated, dopants are ion implanted into the strained mono-crystalline semiconductor region (22) to minimize implant related damage. Thereafter the substrate (16) is heated under non-steady state conditions for a time sufficient to activate the implanted dopant and anneal implant related damage while minimizing relaxation of the strained heterojunction.
摘要翻译：掺杂应变异质结半导体器件的方法包括将具有应变单晶半导体区域（22）的衬底（16）加热到高于室温的温度。当衬底（16）被加热时，掺杂剂被离子注入到应变单晶半导体区域（22）中，以最小化植入物相关损伤。此后，衬底（16）在非稳态条件下被加热足以激活注入的掺杂剂并退火植入物相关损伤的时间，同时最小化应变异质结的松弛。

4. 发明授权

US5498578A Method for selectively forming semiconductor regions 失效
标题翻译：选择性地形成半导体区域的方法
公开(公告)号：US5498578A
公开(公告)日：1996-03-12
申请号：US236054
申请日：1994-05-02
申请人： John W. Steele , Edouard de Fresart , N. David Theodore
发明人： John W. Steele , Edouard de Fresart , N. David Theodore
IPC分类号： H01L21/205 , H01L21/20 , H01L27/06 , H01L21/02
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02661 , H01L27/0623
摘要： A method for selectively forming semiconductor regions (28) is provided, by exposing a patterned substrate (21) having exposed regions of semiconductor material (26,27) and exposed regions of oxide (24) to a first temperature and a semiconductor source-gas and hydrogen in an atmosphere substantially absent halogens, a blanket semiconductor layer (28,29) forms over the exposed regions of semiconductor material (26,27) and oxide (24). By further exposing the patterned substrate (21) to a second temperature higher than the first temperature in a hydrogen atmosphere, polycrystalline semiconductor material (29) formed over the exposed oxide regions (24) is selectively removed leaving that portion of the blanket semiconductor layer (28) over the exposed regions of semiconductor material (26,27). The method is suitable for forming isolated regions of semiconductor material for fabricating semiconductor devices and is not load dependent.
摘要翻译：提供一种用于选择性地形成半导体区域（28）的方法，通过将具有暴露的半导体材料（26,27）区域和氧化物（24）的暴露区域的图案化衬底（21）暴露于第一温度和半导体源气体和基本上不含卤素的气氛中的氢气，覆盖半导体层（28,29）形成在半导体材料（26,27）和氧化物（24）的暴露区域上。通过在氢气氛中将图案化的衬底（21）进一步暴露于高于第一温度的第二温度下，形成在暴露的氧化物区域（24）上方的多晶半导体材料（29）被选择性地去除，留下覆盖半导体层 28）暴露在半导体材料（26,27）的区域上。该方法适用于形成用于制造半导体器件的半导体材料的隔离区域，并且不依赖负载。

5. 发明授权

US5436180A Method for reducing base resistance in epitaxial-based bipolar transistor 失效
标题翻译：降低外延双极晶体管的基极电阻的方法
公开(公告)号：US5436180A
公开(公告)日：1995-07-25
申请号：US203094
申请日：1994-02-28
申请人： Edouard D. de Fresart , John W. Steele , N. David Theodore
发明人： Edouard D. de Fresart , John W. Steele , N. David Theodore
IPC分类号： H01L21/316 , H01L21/20 , H01L21/331 , H01L29/10 , H01L29/73 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , Y10S148/011
摘要： One preferred method for making a semiconductor structure includes altering the direction, and optionally the position, of a polycrystalline grain boundary (38) in a base layer (17,21) of an epitaxial base bipolar transistor (10). Altering the grain boundary (38) may be accomplished by annealing the semiconductor structure after the layer, which later forms the lower portion of the base (17), has been deposited. Altering the grain boundary (38) has a significant effect in reducing base resistance (R.sub.bx1, R.sub.bx2). Reduced base resistance (R.sub.bx1, R.sub.bx2) dramatically improves device performance.
摘要翻译：用于制造半导体结构的一个优选方法包括改变外延基极双极晶体管（10）的基极层（17,21）中的多晶晶界（38）的方向和任选的位置。改变晶界（38）可以通过在后面形成基底（17）的下部的层已经沉积的层之后退火半导体结构来实现。改变晶界（38）对降低碱电阻（Rbx1，Rbx2）具有显着的影响。降低基极电阻（Rbx1，Rbx2）显着提高器件性能。

6. 发明授权

US5326971A Transmission electron microscope environmental specimen holder 失效
标题翻译：透射电子显微镜环境标本架
公开(公告)号：US5326971A
公开(公告)日：1994-07-05
申请号：US62262
申请日：1993-05-17
申请人： N. David Theodore , Juan P. Carrejo
发明人： N. David Theodore , Juan P. Carrejo
IPC分类号： H01J37/20 , H01J37/295 , H01J37/30
CPC分类号： H01J37/20 , H01J37/26 , H01J2237/2003
摘要： An environmental chamber for a transmission electron microscope, in which a specimen is held in position within the transmission electron microscope so an electron beam passes through the specimen to a detector. A removable sleeve surrounds the specimen holder and is sealed at both ends by a seal between the removable sleeve and the specimen holder to form a differential pressure chamber. Apertures are formed in the removable sleeve allowing the electron beam to pass through the specimen to the detector. A vacuum line allows gases to be removed from the differential chamber. A reactive inlet line extends into the differential chamber to allow a material to be introduced onto the specimen.
摘要翻译：一种用于透射电子显微镜的环境室，其中将样品保持在透射电子显微镜内就位，使得电子束通过样品到达检测器。可拆卸的套筒围绕样品保持器，并通过可拆卸套筒和样品架之间的密封件在两端密封，以形成差压室。孔可形成在可拆卸的套筒中，允许电子束通过样本到检测器。真空管路允许气体从差速器室中移出。反应性入口管线延伸到差速器室中，以允许将材料引入到样品上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式