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1. 发明授权

US09379275B2 Apparatus and method for reducing dark current in image sensors 有权
标题翻译：降低图像传感器暗电流的装置和方法
公开(公告)号：US09379275B2
公开(公告)日：2016-06-28
申请号：US13436364
申请日：2012-03-30
申请人： Miao-Cheng Liao , Jinn-Kwei Liang , Wen-Chieh Hsieh , Shiu-Ko JangJian , Hsiang Hsiang Ko , Ying-Lang Wang
发明人： Miao-Cheng Liao , Jinn-Kwei Liang , Wen-Chieh Hsieh , Shiu-Ko JangJian , Hsiang Hsiang Ko , Ying-Lang Wang
IPC分类号： H01L31/18 , H01L31/103 , H01L27/146
CPC分类号： H01L31/1804 , H01L27/1462 , H01L27/1464 , H01L31/103 , Y02E10/547 , Y02P70/521
摘要： A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.
摘要翻译：一种用于减小图像传感器中的暗电流的方法包括提供背面照射的图像传感器晶片，在背面照射的图像传感器晶片的背面上沉积第一钝化层，在第一钝化层上沉积等离子体增强的钝化层并沉积第二钝化层层上的等离子体增强钝化层。

2. 发明申请

US20130193540A1 Apparatus and Method for Reducing Dark Current in Image Sensors 有权
标题翻译：降低图像传感器暗电流的装置和方法
公开(公告)号：US20130193540A1
公开(公告)日：2013-08-01
申请号：US13436364
申请日：2012-03-30
申请人： Miao-Cheng Liao , Jinn-Kwei Liang , Wen-Chieh Hsieh , Shiu-Ko JangJian , Hsiang Hsiang Ko , Ying-Lang Wang
发明人： Miao-Cheng Liao , Jinn-Kwei Liang , Wen-Chieh Hsieh , Shiu-Ko JangJian , Hsiang Hsiang Ko , Ying-Lang Wang
IPC分类号： H01L31/0232 , H01L31/0216
CPC分类号： H01L31/1804 , H01L27/1462 , H01L27/1464 , H01L31/103 , Y02E10/547 , Y02P70/521
摘要： A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.
摘要翻译：一种用于减小图像传感器中的暗电流的方法包括提供背面照射的图像传感器晶片，在背面照射的图像传感器晶片的背面上沉积第一钝化层，在第一钝化层上沉积等离子体增强的钝化层并沉积第二钝化层层上的等离子体增强钝化层。

3. 发明授权

US08692299B2 Two-step shallow trench isolation (STI) process 有权
标题翻译：两步浅沟槽隔离（STI）工艺
公开(公告)号：US08692299B2
公开(公告)日：2014-04-08
申请号：US13594254
申请日：2012-08-24
申请人： Min Hao Hong , You-Hua Chou , Chih-Tsung Lee , Shiu-Ko JangJian , Miao-Cheng Liao , Hsiang Hsiang Ko , Chen-Ming Huang
发明人： Min Hao Hong , You-Hua Chou , Chih-Tsung Lee , Shiu-Ko JangJian , Miao-Cheng Liao , Hsiang Hsiang Ko , Chen-Ming Huang
IPC分类号： H01L27/085
CPC分类号： H01L21/76224 , H01L21/02538 , H01L21/02609 , H01L21/0334 , H01L21/31053 , H01L21/762 , H01L21/76232 , H01L21/823412 , H01L21/823481 , H01L29/0653 , H01L29/66477 , H01L29/66651 , H01L29/78
摘要： An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.
摘要翻译：集成电路器件和用于制造集成电路器件的工艺。集成电路器件包括其中形成有沟槽的衬底，占据沟槽的隔离材料的第一层，在第一隔离材料层上形成的隔离材料的第二层，衬底上的外延生长的硅层，并且水平相邻第二层隔离材料，以及形成在外延生长的硅上的栅极结构，栅极结构限定沟道。

4. 发明申请

US20120292639A1 STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING 有权
标题翻译：应力半导体器件及其制造方法
公开(公告)号：US20120292639A1
公开(公告)日：2012-11-22
申请号：US13111732
申请日：2011-05-19
申请人： Miao-Cheng Liao , Min Hao Hong , Hsiang Hsiang Ko , Kei-Wei Chen , Ying-Lang Wang
发明人： Miao-Cheng Liao , Min Hao Hong , Hsiang Hsiang Ko , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L29/06 , H01L29/24 , H01L21/762
CPC分类号： H01L21/823807 , H01L21/0245 , H01L21/02529 , H01L21/02532 , H01L21/0262
摘要： A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.
摘要翻译：公开了一种制造半导体器件的半导体器件和方法。用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。该方法包括提供衬底并在衬底上形成电介质层。该方法还包括在电介质层内形成第一沟槽，其中第一沟槽延伸穿过电介质层并且外延（epi）在第一沟槽内生长第一有源层，并用辐射能选择性地固化与第一沟槽相邻的介电层活动层

5. 发明授权

US08455883B2 Stressed semiconductor device and method of manufacturing 有权
标题翻译：强调半导体器件及其制造方法
公开(公告)号：US08455883B2
公开(公告)日：2013-06-04
申请号：US13111732
申请日：2011-05-19
申请人： Miao-Cheng Liao , Min Hao Hong , Hsiang Hsiang Ko , Kei-Wei Chen , Ying-Lang Wang
发明人： Miao-Cheng Liao , Min Hao Hong , Hsiang Hsiang Ko , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L29/15 , H01L31/052 , H01L21/331
CPC分类号： H01L21/823807 , H01L21/0245 , H01L21/02529 , H01L21/02532 , H01L21/0262
摘要： A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.
摘要翻译：公开了一种制造半导体器件的半导体器件和方法。用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。该方法包括提供衬底并在衬底上形成电介质层。该方法还包括在电介质层内形成第一沟槽，其中第一沟槽延伸穿过电介质层并且外延（epi）在第一沟槽内生长第一有源层，并用辐射能选择性地固化与第一沟槽相邻的介电层活动层

6. 发明申请

US20130069233A1 Reverse Damascene Process 有权
公开(公告)号：US20130069233A1
公开(公告)日：2013-03-21
申请号：US13234299
申请日：2011-09-16
申请人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
发明人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/768 , H01L21/76841 , H01L21/76852 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.

7. 发明授权

US08518818B2 Reverse damascene process 有权
标题翻译：反向镶嵌工艺
公开(公告)号：US08518818B2
公开(公告)日：2013-08-27
申请号：US13234299
申请日：2011-09-16
申请人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
发明人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/768 , H01L21/76841 , H01L21/76852 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.
摘要翻译：本公开涉及一种形成后端金属化层的方法。通过在由图案化的光致抗蚀剂层限定的区域内的半导体衬底上形成多个独立金属层结构（即，不被电介质材料包围的金属层结构）来执行该方法。扩散阻挡层以使得扩散阻挡层符合金属层结构的顶部和侧面的方式沉积到金属层结构上。在基板的表面上形成电介质材料以填充金属层结构之间的区域。将衬底平坦化以除去多余的金属和电介质材料并露出金属层结构的顶部。

8. 发明授权

US08735255B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08735255B2
公开(公告)日：2014-05-27
申请号：US13461532
申请日：2012-05-01
申请人： Wen Chu Hsiao , Lai Wan Chong , Chun-Chieh Wang , Ying Min Chou , Hsiang Hsiang Ko , Ying-Lang Wang
发明人： Wen Chu Hsiao , Lai Wan Chong , Chun-Chieh Wang , Ying Min Chou , Hsiang Hsiang Ko , Ying-Lang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/28518 , H01L29/0603 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/66515 , H01L29/6653 , H01L29/66636 , H01L29/7845 , H01L29/7847
摘要： In a method of manufacturing a semiconductor device, a source/drain feature is formed over a substrate. A Si-containing layer is formed over the source/drain feature. A metal layer is formed over the Si-containing layer. A metal silicide layer is formed from the metal layer and Si in the Si-containing layer.
摘要翻译：在制造半导体器件的方法中，在衬底上形成源极/漏极特征。在源极/漏极特征上形成含Si层。在含Si层上形成金属层。金属硅化物层由金属层和含Si层中的Si形成。

9. 发明授权

US09064892B2 Semiconductor devices utilizing partially doped stressor film portions and methods for forming the same 有权
标题翻译：利用部分掺杂的应力膜部分的半导体器件及其形成方法
公开(公告)号：US09064892B2
公开(公告)日：2015-06-23
申请号：US13221160
申请日：2011-08-30
申请人： Wen Chu Hsiao , Ju Wen Hsiao , Ying Min Chou , Hsiang Hsiang Ko , Ying-Lang Wang
发明人： Wen Chu Hsiao , Ju Wen Hsiao , Ying Min Chou , Hsiang Hsiang Ko , Ying-Lang Wang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/165
CPC分类号： H01L29/66636 , H01L21/02529 , H01L21/02532 , H01L21/02535 , H01L21/0262 , H01L21/30604 , H01L29/165 , H01L29/167 , H01L29/7834 , H01L29/7848
摘要： A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.
摘要翻译：半导体结构及其形成方法提供适合用作源极/漏极区域或其它有源器件的高迁移率应力源材料。该结构形成在衬底开口中，并且在上部掺杂有诸如硼的杂质，但是在与开口的表面接触的区域中不含杂质。因此，该结构在高温操作期间抵抗掺杂剂杂质的扩散，并且可以通过使用减压化学气相沉积或减压外延沉积的选择性沉积来形成。

10. 发明申请

US20100255187A1 Devices having a cavity structure and related methods 有权
标题翻译：具有腔结构和相关方法的器件
公开(公告)号：US20100255187A1
公开(公告)日：2010-10-07
申请号：US12662681
申请日：2010-04-28
申请人： You-Hua Chou , Hsiang Hsiang Ko , Hung Jui Chang , Yi Ming Chen , Hsien-Wei Lin
发明人： You-Hua Chou , Hsiang Hsiang Ko , Hung Jui Chang , Yi Ming Chen , Hsien-Wei Lin
IPC分类号： B05D5/12
CPC分类号： H01M8/1097 , H01M2008/1095 , Y02P70/56
摘要： A structure having a cavity or enclosed space is fabricated by forming a recessed region in a surface of a substrate, and providing a first layer adjacent the recessed region. A liquid mixture including first and second components is supplied to the recessed region. The first component has a higher chemical affinity to the first layer than the second component such that the first component separates from the second component and adheres to an edge portion of the first layer. The substrate may then be heated to remove the second component from the recessed region through evaporation. As a result, the first component remains as a second layer adhering to the edge portion of the first layer and covering the recessed region, thereby defining a cavity or enclosed space with the recessed region. Unique structures including such cavities may be employed to realize a capacitor having a fluid, as opposed to solid, dielectric material, in order to increase the capacitance of the capacitor. Alternatively, such cavities may confine the flow of gases within narrow grooves of a substrate to realize a fuel cell having reduced size.
摘要翻译：通过在衬底的表面中形成凹陷区域并且提供与凹陷区域相邻的第一层来制造具有空腔或封闭空间的结构。包含第一和第二组分的液体混合物被供应到凹陷区域。第一组分比第二组分具有比第一组分更高的化学亲和力，使得第一组分与第二组分分离并粘附到第一层的边缘部分。然后可以加热衬底以通过蒸发从凹陷区域去除第二组分。结果，第一部件保持作为粘附到第一层的边缘部分并覆盖凹陷区域的第二层，由此限定具有凹陷区域的空腔或封闭空间。包括这种空穴的独特结构可以用于实现与固体介电材料相反的流体的电容器，以便增加电容器的电容。或者，这样的空腔可以将气体流限制在基板的窄槽内，以实现具有减小的尺寸的燃料电池。

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