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1. 发明申请

US20070170488A1 Capacitor of semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体器件的电容器及其制造方法
公开(公告)号：US20070170488A1
公开(公告)日：2007-07-26
申请号：US11655944
申请日：2007-01-22
申请人： Mi-Young Ryu , Hee-Il Chae
发明人： Mi-Young Ryu , Hee-Il Chae
IPC分类号： H01L27/108 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10852
摘要： A capacitor of a semiconductor device and a method for fabricating the same may be provided. The method may include forming an interlayer insulation layer, an etch stop layer, and/or a sacrificial insulation layer on a semiconductor substrate, patterning the interlayer insulation layer, the etch stop layer, and/or the sacrificial insulation layer to form a contact hole exposing a desired or predetermined region of the semiconductor substrate, filling the contact hole to form a contact plug, removing the sacrificial insulation layer to expose an upper portion of the contact plug, and/or forming a dielectric layer and/or a top electrode on the exposed upper portion of the contact plug.
摘要翻译：可以提供半导体器件的电容器及其制造方法。该方法可以包括在半导体衬底上形成层间绝缘层，蚀刻停止层和/或牺牲绝缘层，图案化层间绝缘层，蚀刻停止层和/或牺牲绝缘层以形成接触孔暴露半导体衬底的期望或预定区域，填充接触孔以形成接触插塞，去除牺牲绝缘层以暴露接触插塞的上部，和/或形成电介质层和/或顶部电极接触塞的暴露的上部。

2. 发明授权

US07525143B2 Dram device having capacitor 失效
标题翻译：具有电容器的设备
公开(公告)号：US07525143B2
公开(公告)日：2009-04-28
申请号：US11302702
申请日：2005-12-14
申请人： Hee-Il Chae
发明人： Hee-Il Chae
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/10814 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L28/91
摘要： In a DRAM device having a capacitor and a method thereof, the capacitor included in the device is characterized to have a lower electrode that passes through a plurality of interlayer insulating layers. A first interlayer insulating layer is formed on a semiconductor substrate. A first contact plug layer is formed through the first interlayer insulating to electrically contact the semiconductor substrate. An insulating layer is formed on the first interlayer insulating layer. The insulating layer is etched to form the first interlayer insulating layer and a temporary storage node hole exposing the first contact plug. The first interlayer insulating layer exposed by the temporary storage node hole and portions of the first contact plug are simultaneously etched to form a storage node hole. A lower electrode layer is conformally formed on a surface of the semiconductor substrate having the storage node hole. A planarization process is performed with respect to the lower electrode layer to remove the lower electrode layer on the insulating layer and simultaneously to form a cup-shaped lower electrode in the storage node hole. Furthermore, a dielectric layer and an upper electrode are formed to cover conformally and sequentially at least a bottom and inner sidewall of the cup-shaped lower electrode.
摘要翻译：在具有电容器的DRAM器件及其方法中，包括在器件中的电容器的特征在于具有穿过多个层间绝缘层的下电极。第一层间绝缘层形成在半导体衬底上。通过第一层间绝缘体形成第一接触插塞层，以电接触半导体衬底。绝缘层形成在第一层间绝缘层上。蚀刻绝缘层以形成第一层间绝缘层和暴露第一接触插塞的临时存储节点孔。由临时存储节点孔和第一接触插塞的部分暴露的第一层间绝缘层被同时蚀刻以形成存储节点孔。在具有存储节点孔的半导体衬底的表面上共形地形成下电极层。对于下部电极层进行平坦化处理，以除去绝缘层上的下部电极层，同时在存储节点孔中形成杯状的下部电极。此外，形成电介质层和上电极以覆盖杯形下电极的至少底部和内侧壁的顺应性和顺序地覆盖。

3. 发明申请

US20060131632A1 Dram device having capacitor and method thereof 失效
标题翻译：具有电容器的方法及其方法
公开(公告)号：US20060131632A1
公开(公告)日：2006-06-22
申请号：US11302702
申请日：2005-12-14
申请人： Hee-Il Chae
发明人： Hee-Il Chae
IPC分类号： H01L21/8244
CPC分类号： H01L27/10894 , H01L27/10814 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L28/91
摘要： In a DRAM device having a capacitor and a method thereof, the capacitor included in the device is characterized to have a lower electrode that passes through a plurality of interlayer insulating layers. A first interlayer insulating layer is formed on a semiconductor substrate. A first contact plug layer is formed through the first interlayer insulating to electrically contact the semiconductor substrate. An insulating layer is formed on the first interlayer insulating layer. The insulating layer is etched to form the first interlayer insulating layer and a temporary storage node hole exposing the first contact plug. The first interlayer insulating layer exposed by the temporary storage node hole and portions of the first contact plug are simultaneously etched to form a storage node hole. A lower electrode layer is conformally formed on a surface of the semiconductor substrate having the storage node hole. A planarization process is performed with respect to the lower electrode layer to remove the lower electrode layer on the insulating layer and simultaneously to form a cup-shaped lower electrode in the storage node hole. Furthermore, a dielectric layer and an upper electrode are formed to cover conformally and sequentially at least a bottom and inner sidewall of the cup-shaped lower electrode.
摘要翻译：在具有电容器的DRAM器件及其方法中，包括在器件中的电容器的特征在于具有穿过多个层间绝缘层的下电极。第一层间绝缘层形成在半导体衬底上。通过第一层间绝缘体形成第一接触插塞层，以电接触半导体衬底。绝缘层形成在第一层间绝缘层上。蚀刻绝缘层以形成第一层间绝缘层和暴露第一接触插塞的临时存储节点孔。由临时存储节点孔和第一接触插塞的部分暴露的第一层间绝缘层被同时蚀刻以形成存储节点孔。在具有存储节点孔的半导体衬底的表面上共形地形成下电极层。对于下部电极层进行平坦化处理，以除去绝缘层上的下部电极层，同时在存储节点孔中形成杯状的下部电极。此外，形成电介质层和上电极以覆盖杯形下电极的至少底部和内侧壁的顺应性和顺序地覆盖。

4. 发明授权

US07262452B2 Method of forming DRAM device having capacitor and DRAM device so formed 失效
标题翻译：形成具有电容器和DRAM器件的DRAM器件的形成方法
公开(公告)号：US07262452B2
公开(公告)日：2007-08-28
申请号：US11301962
申请日：2005-12-13
申请人： Hee-Il Chae
发明人： Hee-Il Chae
IPC分类号： H01L27/108
CPC分类号： H01L27/10835 , H01L28/90
摘要： In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate are sequentially etched to form a storage node hole. A lower electrode is conformally formed in the storage node hole and on the interlayer dielectric layer. A planarization process is performed to remove a portion of the lower electrode layer that lies on the interlayer dielectric layer and to form a lower electrode in the storage node hole. A dielectric layer and an upper electrode layer are sequentially formed on the lower electrode. The upper electrode layer and the dielectric layer are sequentially patterned.
摘要翻译：在形成具有如此形成的电容器和DRAM器件的DRAM器件的方法中，在半导体衬底上形成具有至少一层的层间电介质。依次蚀刻层间绝缘层和半导体衬底的预定部分以形成存储节点孔。下部电极保形地形成在存储节点孔和层间介质层上。进行平面化处理以去除位于层间电介质层上的下电极层的一部分并在存储节点孔中形成下电极。电介质层和上电极层依次形成在下电极上。上电极层和电介质层依次构图。

5. 发明申请

US20060138516A1 Method of forming DRAM device having capacitor and DRAM device so formed 失效
标题翻译：形成具有电容器和DRAM器件的DRAM器件的形成方法
公开(公告)号：US20060138516A1
公开(公告)日：2006-06-29
申请号：US11301962
申请日：2005-12-13
申请人： Hee-Il Chae
发明人： Hee-Il Chae
IPC分类号： H01L29/94
CPC分类号： H01L27/10835 , H01L28/90
摘要： In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate are sequentially etched to form a storage node hole. A lower electrode is conformally formed in the storage node hole and on the interlayer dielectric layer. A planarization process is performed to remove a portion of the lower electrode layer that lies on the interlayer dielectric layer and to form a lower electrode in the storage node hole. A dielectric layer and an upper electrode layer are sequentially formed on the lower electrode. The upper electrode layer and the dielectric layer are sequentially patterned.
摘要翻译：在形成具有如此形成的电容器和DRAM器件的DRAM器件的方法中，在半导体衬底上形成具有至少一层的层间电介质。依次蚀刻层间绝缘层和半导体衬底的预定部分以形成存储节点孔。下部电极保形地形成在存储节点孔和层间介质层上。进行平面化处理以去除位于层间电介质层上的下电极层的一部分并在存储节点孔中形成下电极。电介质层和上电极层依次形成在下电极上。上电极层和电介质层依次构图。

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