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1. 发明授权

US10234506B2 Continuous application and decompression of test patterns and selective compaction of test responses 有权
公开(公告)号：US10234506B2
公开(公告)日：2019-03-19
申请号：US15608716
申请日：2017-05-30
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3183 , G01R31/3185
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

2. 发明授权

US09651622B2 Isometric test compression with low toggling activity 有权
公开(公告)号：US09651622B2
公开(公告)日：2017-05-16
申请号：US14642501
申请日：2015-03-09
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Amit Kumar , Mark A. Kassab , Elham Moghaddam , Nilanjan Mukherjee , Jerzy Tyszer , Chen Wang
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/3185
CPC分类号： G01R31/318342 , G01R31/318547 , G01R31/318583
摘要： Various aspects of the disclosed technology relate to techniques of creating test templates for test pattern generation. Residual test cubes for a plurality of faults are first generated based on a signal probability analysis of a circuit design. Test templates are then generated based on merging the residual test cubes. Finally, a plurality of test patterns and/or compressed test cubes are generated based on one of the test templates.

3. 发明授权

US09134370B2 Continuous application and decompression of test patterns and selective compaction of test responses 有权
标题翻译：测试模式的连续应用和减压以及测试响应的选择性压缩
公开(公告)号：US09134370B2
公开(公告)日：2015-09-15
申请号：US14021800
申请日：2013-09-09
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/3183 , G01R31/319
CPC分类号： G01R31/3177 , G01R31/318335 , G01R31/318547 , G01R31/31921
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的位测试模式的线性有限状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。

4. 发明申请

US20150160290A1 ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES 有权
标题翻译：片上比较和响应收集工具和技术
公开(公告)号：US20150160290A1
公开(公告)日：2015-06-11
申请号：US14570731
申请日：2014-12-15
申请人： MENTOR GRAPHICS CORPORATION
发明人： Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供大约1000×的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

5. 发明授权

US10444282B2 Test point insertion for low test pattern counts 有权
公开(公告)号：US10444282B2
公开(公告)日：2019-10-15
申请号：US14884611
申请日：2015-10-15
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Elham K. Moghaddam , Nilanjan Mukherjee , Jerzy Tyszer , Justyna Zawada
IPC分类号： G06F17/50 , G01R31/3183
摘要： Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.

6. 发明授权

US10120024B2 Multi-stage test response compactors 有权
公开(公告)号：US10120024B2
公开(公告)日：2018-11-06
申请号：US15723112
申请日：2017-10-02
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Mark Kassab , Wu-Tung Cheng
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185 , G01R31/317
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

7. 发明授权

US09377508B2 Selective per-cycle masking of scan chains for system level test 有权
标题翻译：用于系统级测试的扫描链选择性每周期屏蔽
公开(公告)号：US09377508B2
公开(公告)日：2016-06-28
申请号：US14257918
申请日：2014-04-21
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3185 , G06F11/27
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
摘要翻译：用于处理未知状态问题的集成电路的内置自检技术。一些实现使用与时间压缩器相连的专用扫描链选择器。专门的扫描链选择器的存在提高了掩蔽X状态的效率。还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3）以处理过度掩蔽现象。

8. 发明申请

US20160109517A1 Test Point Insertion For Low Test Pattern Counts 审中-公开
标题翻译：测试点插入低测试图案计数
公开(公告)号：US20160109517A1
公开(公告)日：2016-04-21
申请号：US14884611
申请日：2015-10-15
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Elham K. Moghaddam , Nilanjan Mukherjee , Jerzy Tyszer , Justyna Zawada
IPC分类号： G01R31/3177
CPC分类号： G01R31/318307 , G01R31/318342 , G01R31/318371
摘要： Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.
摘要翻译：所公开技术的各个方面涉及减少冲突的测试点插入技术。用于插入测试点的电路设计中的位置是基于通过使用单个测试图案检测多个故障引起的内部信号冲突来确定的。然后将测试点插入位置。内部信号冲突可能包括横向冲突，垂直冲突或两者。测试点可以包括控制点，观测点或两者。

9. 发明授权

US09250287B2 On-chip comparison and response collection tools and techniques 有权
标题翻译：片上比较和响应收集工具和技术
公开(公告)号：US09250287B2
公开(公告)日：2016-02-02
申请号：US14570731
申请日：2014-12-15
申请人： Mentor Graphics Corporation
发明人： Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供大约1000×的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

10. 发明授权

US11150299B2 Flexible isometric decompressor architecture for test compression 有权
公开(公告)号：US11150299B2
公开(公告)日：2021-10-19
申请号：US16982299
申请日：2019-03-21
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Yu Huang , Sylwester Milewski , Jerzy Tyszer
IPC分类号： G01R31/3185 , G01R31/3181
摘要： A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.

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