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1. 发明授权

US10830815B2 Signal probability-based test cube reordering and merging 有权
公开(公告)号：US10830815B2
公开(公告)日：2020-11-10
申请号：US16360691
申请日：2019-03-21
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Yu Huang
IPC分类号： G01R31/30 , G01R31/3177 , G01R31/317
摘要： A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of “1” and a specified value of “0” for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.

2. 发明申请

US20200327268A1 Scan Cell Architecture For Improving Test Coverage And Reducing Test Application Time 审中-公开
公开(公告)号：US20200327268A1
公开(公告)日：2020-10-15
申请号：US16845139
申请日：2020-04-10
申请人： Mentor Graphics Corporation
发明人： Nilanjan Mukherjee , Jedrzej Solecki , Janusz Rajski
IPC分类号： G06F30/333 , G01R31/3177
摘要： A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.

3. 发明授权

US10234506B2 Continuous application and decompression of test patterns and selective compaction of test responses 有权
公开(公告)号：US10234506B2
公开(公告)日：2019-03-19
申请号：US15608716
申请日：2017-05-30
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3183 , G01R31/3185
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

4. 发明授权

US09915702B2 Channel sharing for testing circuits having non-identical cores 有权
公开(公告)号：US09915702B2
公开(公告)日：2018-03-13
申请号：US14554898
申请日：2014-11-26
申请人： Mentor Graphics Corporation
发明人： Yu Huang , Mark A. Kassab , Janusz Rajski , Wu-Tung Cheng , Jay Babak Jahangiri
IPC分类号： G01R31/28 , G01R31/3183
CPC分类号： G01R31/318335
摘要： Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.

5. 发明授权

US09651622B2 Isometric test compression with low toggling activity 有权
公开(公告)号：US09651622B2
公开(公告)日：2017-05-16
申请号：US14642501
申请日：2015-03-09
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Amit Kumar , Mark A. Kassab , Elham Moghaddam , Nilanjan Mukherjee , Jerzy Tyszer , Chen Wang
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/3185
CPC分类号： G01R31/318342 , G01R31/318547 , G01R31/318583
摘要： Various aspects of the disclosed technology relate to techniques of creating test templates for test pattern generation. Residual test cubes for a plurality of faults are first generated based on a signal probability analysis of a circuit design. Test templates are then generated based on merging the residual test cubes. Finally, a plurality of test patterns and/or compressed test cubes are generated based on one of the test templates.

6. 发明授权

US09568552B2 Logic built-in self-test with high test coverage and low switching activity 有权
标题翻译：逻辑内置自检，测试覆盖率高，开关活动低
公开(公告)号：US09568552B2
公开(公告)日：2017-02-14
申请号：US14298663
申请日：2014-06-06
申请人： Mentor Graphics Corporation
发明人： Xijiang Lin , Janusz Rajski
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3183
CPC分类号： G01R31/318575 , G01R31/318385 , G01R31/318547
摘要： The test circuitry according to various aspects of the presently disclosed techniques comprises: low-toggling pseudo-random test pattern generation circuitry, wherein the low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator; scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry; background chains configurable to shift in a background test pattern; and weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern.
摘要翻译：根据当前公开的技术的各个方面的测试电路包括：低切换伪随机测试模式生成电路，其中由低切换伪随机测试模式产生电路产生的低切换伪随机测试模式引起切换在扫描移位周期期间的活动低于由伪随机模式发生器产生的伪随机测试模式; 扫描链可配置为在由低切换伪随机测试图案生成电路产生的低切换伪随机测试图案中移位; 背景链可配置为在背景测试模式中移动; 以及加权插入电路，其可配置为基于所述背景测试图案中的比特来修改所述低切换伪随机测试模式中的多个比特，以形成加权的伪随机测试模式。

7. 发明授权

US09335374B2 Dynamic shift for test pattern compression 有权
标题翻译：测试模式压缩的动态移位
公开(公告)号：US09335374B2
公开(公告)日：2016-05-10
申请号：US14557739
申请日：2014-12-02
申请人： Mentor Graphics Corporation
发明人： Xijiang Lin , Mark A. Kassab , Janusz Rajski
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536 , G01R31/318547
摘要： Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.
摘要翻译：所公开的技术的各个方面涉及使用用于测试图案压缩的动态移位。扫描链分为几段。非移位时钟周期被添加到一个或多个段以使不可压缩的测试图案可压缩。可以基于可压缩性，指定位的数量和/或扫描链上的位置来选择一个或多个段。可以采用动态变速控制器来控制动态位移。

8. 发明授权

US09134370B2 Continuous application and decompression of test patterns and selective compaction of test responses 有权
标题翻译：测试模式的连续应用和减压以及测试响应的选择性压缩
公开(公告)号：US09134370B2
公开(公告)日：2015-09-15
申请号：US14021800
申请日：2013-09-09
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/3183 , G01R31/319
CPC分类号： G01R31/3177 , G01R31/318335 , G01R31/318547 , G01R31/31921
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的位测试模式的线性有限状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。

9. 发明申请

US20150160290A1 ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES 有权
标题翻译：片上比较和响应收集工具和技术
公开(公告)号：US20150160290A1
公开(公告)日：2015-06-11
申请号：US14570731
申请日：2014-12-15
申请人： MENTOR GRAPHICS CORPORATION
发明人： Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供大约1000×的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

10. 发明申请

US20150149847A1 Channel Sharing For Testing Circuits Having Non-Identical Cores 有权
标题翻译：用于具有不相同核心的测试电路的通道共享
公开(公告)号：US20150149847A1
公开(公告)日：2015-05-28
申请号：US14554898
申请日：2014-11-26
申请人： Mentor Graphics Corporation
发明人： Yu Huang , Mark A. Kassab , Janusz Rajski , Wu-Tung Cheng , Jay Babak Jahangiri
IPC分类号： G01R31/3177 , G01R31/3183
CPC分类号： G01R31/318335
摘要： Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.
摘要翻译：所公开技术的各个方面涉及用于测试具有不相同核心的电路的信道共享技术。生成用于多个电路块的压缩测试图案用于信道共享。多个电路块中的每一个包括被配置为解压缩压缩的测试图案的解压缩器。因此，测试数据输入通道由解压缩器共享。控制数据输入通道通常不被多个电路块中的不相同的电路块共享。

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