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1. 发明申请

US20090190631A1 METHOD FOR GENERATING A SPREAD SPECTRUM CLOCK AND APPARATUS THEREOF 有权
标题翻译：用于产生传播频谱时钟的方法及其装置
公开(公告)号：US20090190631A1
公开(公告)日：2009-07-30
申请号：US12358261
申请日：2009-01-23
申请人： Meng-Han Hsieh , Chi-Shun Weng , Ming-Je Li , Kai-Yi Fang
发明人： Meng-Han Hsieh , Chi-Shun Weng , Ming-Je Li , Kai-Yi Fang
IPC分类号： H04B1/69
CPC分类号： H04B1/69 , G06F1/04
摘要： A method for generating a spread spectrum clock includes the steps of providing a reference clock having a reference period; generating a plurality of output clocks respectively having different phases according to the reference clock; generating a first/second control signal according to the reference clock and a spread spectrum clock and starting a first/second duration accordingly; during the first/second duration, outputting a first/second selecting signal representing a first/second predetermined sequence according to the first/second control signal, wherein the second predetermined sequence is a substantial reversed sequence of the first predetermined sequence; and during the first/second duration, sequentially outputting some or all of the output clocks as the spread spectrum clock according to the first/second predetermined sequence.
摘要翻译：一种用于产生扩频时钟的方法包括以下步骤：提供具有参考周期的参考时钟; 根据参考时钟产生分别具有不同相位的多个输出时钟; 根据参考时钟和扩频时钟产生第一/第二控制信号并相应地开始第一/第二持续时间; 在第一/第二持续时间期间，根据第一/第二控制信号输出表示第一/第二预定序列的第一/第二选择信号，其中第二预定序列是第一预定序列的实质上相反的顺序; 并且在第一/第二持续时间期间，根据第一/第二预定序列顺序地输出部分或全部输出时钟作为扩频时钟。

2. 发明授权

US09473344B2 Circuit and method for setting data and their application to integrated circuit 有权
标题翻译：用于设置数据的电路和方法及其在集成电路中的应用
公开(公告)号：US09473344B2
公开(公告)日：2016-10-18
申请号：US12340443
申请日：2008-12-19
申请人： Ming-Yuh Yeh , Chi-Shun Weng , Ming-Je Li , Kai-Yi Fang , Meng-Han Hsieh
发明人： Ming-Yuh Yeh , Chi-Shun Weng , Ming-Je Li , Kai-Yi Fang , Meng-Han Hsieh
IPC分类号： G06F3/00 , G06F13/14 , H04L29/12 , G06F13/40 , H04L29/08
CPC分类号： H04L29/12254 , G06F13/4068 , G06F2213/0052 , H04L61/2038 , H04L69/32 , H04L69/324
摘要： An integrated circuit is disclosed, including at least one configuration pin, an interface circuit, a detecting circuit, a determining circuit and a storage unit. A physical layer circuit of the invention not only increases the flexibility of setting PHY addresses, but also reduces the number of configuration pins.
摘要翻译：公开了一种集成电路，包括至少一个配置引脚，接口电路，检测电路，确定电路和存储单元。本发明的物理层电路不仅增加了设置PHY地址的灵活性，而且还减少了配置引脚的数量。

3. 发明授权

US08094698B2 Method for generating a spread spectrum clock and apparatus thereof 有权
标题翻译：用于产生扩频时钟的方法及其装置
公开(公告)号：US08094698B2
公开(公告)日：2012-01-10
申请号：US12358261
申请日：2009-01-23
申请人： Meng-Han Hsieh , Chi-Shun Weng , Ming-Je Li , Kai-Yi Fang
发明人： Meng-Han Hsieh , Chi-Shun Weng , Ming-Je Li , Kai-Yi Fang
IPC分类号： H04B1/69
CPC分类号： H04B1/69 , G06F1/04
摘要： A method for generating a spread spectrum clock includes the steps of providing a reference clock having a reference period; generating a plurality of output clocks respectively having different phases according to the reference clock; generating a first/second control signal according to the reference clock and a spread spectrum clock and starting a first/second duration accordingly; during the first/second duration, outputting a first/second selecting signal representing a first/second predetermined sequence according to the first/second control signal, wherein the second predetermined sequence is a substantial reversed sequence of the first predetermined sequence; and during the first/second duration, sequentially outputting some or all of the output clocks as the spread spectrum clock according to the first/second predetermined sequence.
摘要翻译：一种用于产生扩频时钟的方法包括以下步骤：提供具有参考周期的参考时钟; 根据参考时钟产生分别具有不同相位的多个输出时钟; 根据参考时钟和扩频时钟产生第一/第二控制信号并相应地开始第一/第二持续时间; 在第一/第二持续时间期间，根据第一/第二控制信号输出表示第一/第二预定序列的第一/第二选择信号，其中第二预定序列是第一预定序列的实质上相反的顺序; 并且在第一/第二持续时间期间，根据第一/第二预定序列顺序地输出部分或全部输出时钟作为扩频时钟。

4. 发明申请

US20090164628A1 CIRCUIT AND METHOD FOR SETTING DATA AND THEIR APPLICATION TO INTEGRATED CIRCUIT 有权
标题翻译：用于设置数据的电路和方法及其在集成电路中的应用
公开(公告)号：US20090164628A1
公开(公告)日：2009-06-25
申请号：US12340443
申请日：2008-12-19
申请人： Ming-Yuh YEH , Chi-Shun Weng , Ming-Je Li , Kai-Yi Fang , Meng-Han Hsieh
发明人： Ming-Yuh YEH , Chi-Shun Weng , Ming-Je Li , Kai-Yi Fang , Meng-Han Hsieh
IPC分类号： G06F15/173
CPC分类号： H04L29/12254 , G06F13/4068 , G06F2213/0052 , H04L61/2038 , H04L69/32 , H04L69/324
摘要： An integrated circuit is disclosed, including at least one configuration pin, an interface circuit, a detecting circuit, a determining circuit and a storage unit. A physical layer circuit of the invention not only increases the flexibility of setting PHY addresses, but also reduces the number of configuration pins.
摘要翻译：公开了一种集成电路，包括至少一个配置引脚，接口电路，检测电路，确定电路和存储单元。本发明的物理层电路不仅增加了设置PHY地址的灵活性，而且还减少了配置引脚的数量。

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