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1. 发明授权

US07572734B2 Etch depth control for dual damascene fabrication process 失效
标题翻译：蚀刻深度控制双镶嵌工艺
公开(公告)号：US07572734B2
公开(公告)日：2009-08-11
申请号：US11877964
申请日：2007-10-24
申请人： Mehul Naik , Suketu A. Parikh , Michael D. Armacost
发明人： Mehul Naik , Suketu A. Parikh , Michael D. Armacost
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01J37/32091 , H01J37/3266 , H01J2237/3347 , H01L21/76807 , H01L21/76808 , H01L22/26
摘要： The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading etching process and a reverse micro-loading etching process using two etch chemistries together with the inclusion of a dopant material layer or an organic fill material layer during the deposition of the dielectric film stack. In one embodiment, etching of trenches over vias is switched from forward micro-loading to reverse micro-loading once etching of the dielectric film stack is reached at a predetermined location of a dopant material layer. In another embodiment, etching of an organic trench filling material layer is performed in a reverse micro-loading process followed by etching the dielectric film stack in a forward micro-loading process.
摘要翻译：电介质膜堆叠中的双镶嵌结构的沟槽过孔蚀刻中的蚀刻深度被控制为在基底的致密区域和开放区域上相同，并且解决微加载问题。沟槽蚀刻工艺适于包括使用两个蚀刻化学物质的正向微加载蚀刻工艺和反向微加载蚀刻工艺，以及在沉积介电膜堆叠期间包含掺杂剂材料层或有机填充材料层。在一个实施例中，一旦在掺杂剂材料层的预定位置处达到电介质膜堆叠的蚀刻，则在通孔上的沟槽的蚀刻从正向微负载切换到反向微负载。在另一个实施例中，有机沟槽填充材料层的蚀刻在反向微加载过程中进行，然后在正向微加载过程中蚀刻介电膜堆叠。

2. 发明授权

US07205228B2 Selective metal encapsulation schemes 失效
标题翻译：选择性金属封装方案
公开(公告)号：US07205228B2
公开(公告)日：2007-04-17
申请号：US10812480
申请日：2004-03-30
申请人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
发明人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/288 , H01L21/76829 , H01L21/7685 , H01L21/76885
摘要： A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.
摘要翻译：在一个或多个实施例中，处理半导体衬底的方法和系统包括在衬底表面上沉积保护层，所述保护层包括布置在电介质材料中的导电元件; 处理所述保护层以暴露所述导电元件; 将金属钝化层无电沉积到导电元件上; 以及在无电沉积之后从衬底去除保护层的至少一部分。在另一方面，一种处理半导体的方法和系统包括在包括导电元件的衬底表面上沉积金属钝化层，掩蔽钝化层以保护衬底表面的下面的导电元件，去除未屏蔽的钝化层，以及去除掩模从钝化层。

3. 发明授权

US07115534B2 Dielectric materials to prevent photoresist poisoning 失效
标题翻译：介电材料防止光致抗蚀剂中毒
公开(公告)号：US07115534B2
公开(公告)日：2006-10-03
申请号：US10847891
申请日：2004-05-18
申请人： Son Van Nguyen , Michael D. Armacost , Mehul Naik , Girish A. Dixit , Ellie Y. Yieh
发明人： Son Van Nguyen , Michael D. Armacost , Mehul Naik , Girish A. Dixit , Ellie Y. Yieh
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76808
摘要： Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.
摘要翻译：提供了用于沉积电介质材料的方法，用作防蚀涂层和牺牲电介质材料在镶嵌形成中。在一个方面，提供了一种处理衬底的方法，包括通过使含氧有机硅化合物和酸性化合物反应，在酸性电介质层上沉积光致抗蚀剂材料，并使光致抗蚀剂层图形化，在衬底上沉积酸性介电层。通过蚀刻部分特征定义，沉积酸性电介质材料，蚀刻特征定义的其余部分，然后除去酸性介电材料以形成特征定义，可以将酸性介电层用作形成特征定义的牺牲层。

4. 发明授权

US08283237B2 Fabrication of through-silicon vias on silicon wafers 有权
标题翻译：在硅晶片上制造通硅通孔
公开(公告)号：US08283237B2
公开(公告)日：2012-10-09
申请号：US12978129
申请日：2010-12-23
申请人： Nagarajan Rajagopalan , Ji Ae Park , Ryan Yamase , Shamik Patel , Thomas Nowak , Li-Qun Xia , Bok Hoen Kim , Ran Ding , Jim Baldino , Mehul Naik , Sesh Ramaswami
发明人： Nagarajan Rajagopalan , Ji Ae Park , Ryan Yamase , Shamik Patel , Thomas Nowak , Li-Qun Xia , Bok Hoen Kim , Ran Ding , Jim Baldino , Mehul Naik , Sesh Ramaswami
IPC分类号： H01L21/30 , H01L21/4763 , H01L21/44 , H01L21/31
CPC分类号： H01L24/13 , H01L21/02074 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/3065 , H01L21/31116 , H01L21/67103 , H01L21/67109 , H01L21/6719 , H01L21/6835 , H01L21/68792 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76898 , H01L24/11 , H01L24/742 , H01L2221/68372 , H01L2221/68381 , H01L2224/11002 , H01L2224/11452 , H01L2224/1182 , H01L2224/13562 , H01L2224/1357 , H01L2224/13687 , H01L2224/742 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01068 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/351 , H01L2924/05042 , H01L2924/00
摘要： A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.
摘要翻译：通过硅通孔的制造方法包括通过使用其间的粘合剂层将硅板的前表面粘合到载体上来形成基板，以暴露硅板的背面。氮化硅钝化层沉积在衬底的硅板的暴露的背面上。在硅板中蚀刻多个通孔，通孔包括侧壁和底壁。金属导体沉积在通孔中以形成多个通硅通孔。

5. 发明申请

US20120085733A1 SELF ALIGNED TRIPLE PATTERNING 审中-公开
标题翻译：自对准三重图案
公开(公告)号：US20120085733A1
公开(公告)日：2012-04-12
申请号：US13042060
申请日：2011-03-07
申请人： Bencherki Mebarki , Hao Chen , Kedar Sapre , Anchuan Wang , Tushar Mandrekar , Jingmei Liang , Yongmei Chen , Christopher S. Ngai , Mehul Naik
发明人： Bencherki Mebarki , Hao Chen , Kedar Sapre , Anchuan Wang , Tushar Mandrekar , Jingmei Liang , Yongmei Chen , Christopher S. Ngai , Mehul Naik
IPC分类号： C23F1/02
CPC分类号： H01L21/0337 , H01L21/0338
摘要： Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposited and fills the undercut regions as well as the regions between the heterogeneous stacks. The dielectric layer is anisotropically etched and a conformal spacer is deposited on and between the cores. The spacer is anisotropically etched to leave two spacers between each core. The cores are stripped and the spacers are used together with the remaining hard mask features to pattern the substrate at triple the density of the original pattern.
摘要翻译：本发明的实施例涉及使用自对准三重图案化（SATP）工艺在衬底上形成特征的方法。使用高分辨率光掩模，在光刻系统的光学分辨率附近对一叠层进行图案化。选择性地蚀刻异质堆叠以在覆盖的芯之下切割硬掩模层。在形成期间可流动的介电层被沉积并填充底切区域以及异质堆叠之间的区域。介电层被各向异性地蚀刻，并且保形间隔物沉积在芯之间和之间。间隔物被各向异性蚀刻以在每个芯之间留下两个间隔物。芯被剥离，并且间隔物与剩余的硬掩模特征一起使用以将原始图案的密度的三倍图案化。

6. 发明申请

US20120009796A1 POST-ASH SIDEWALL HEALING 审中-公开
标题翻译：后腰围护理
公开(公告)号：US20120009796A1
公开(公告)日：2012-01-12
申请号：US12909167
申请日：2010-10-21
申请人： Zhenjiang Cui , Anchuan Wang , Mehul Naik , Nitin Ingle , Young Lee , Shankar Venkataraman
发明人： Zhenjiang Cui , Anchuan Wang , Mehul Naik , Nitin Ingle , Young Lee , Shankar Venkataraman
IPC分类号： H01L21/3065
CPC分类号： H01L21/3105 , H01L21/31116 , H01L21/31138 , H01L21/76814
摘要： Methods of decreasing the effective dielectric constant present between two conducting components of an integrated circuit are described. The methods involve the use of a gas phase etch which is selective towards the oxygen-rich portion of the low-K dielectric layer. The etch rate attenuates as the etch process passes through the relatively high-K oxygen-rich portion and reaches the low-K portion. The etch process may be easily timed since the gas phase etch process does not readily remove the desirable low-K portion.
摘要翻译：描述了降低集成电路的两个导电部件之间存在的有效介电常数的方法。该方法包括使用对低K电介质层的富氧部分具有选择性的气相蚀刻。当蚀刻工艺通过较高K富氧部分并达到低K部分时，蚀刻速率衰减。由于气相蚀刻工艺不容易除去所需的低K部分，所以蚀刻工艺可以容易地定时。

7. 发明申请

US20110111604A1 PLASMA SURFACE TREATMENT TO PREVENT PATTERN COLLAPSE IN IMMERSION LITHOGRAPHY 审中-公开
标题翻译：等离子体表面处理，以防止浸渍图中的图案褶皱
公开(公告)号：US20110111604A1
公开(公告)日：2011-05-12
申请号：US13007963
申请日：2011-01-17
申请人： Eui Kyoon Kim , Deenesh Padhi , Huixiong Dai , Mehul Naik , Martin Jay Seamons , Bok Hoen Kim
发明人： Eui Kyoon Kim , Deenesh Padhi , Huixiong Dai , Mehul Naik , Martin Jay Seamons , Bok Hoen Kim
IPC分类号： H01L21/31
CPC分类号： G03F7/091 , G03F7/11
摘要： The present invention comprises a method of reducing photoresist mask collapse when the photoresist mask is dried after immersion development. As feature sizes continue to shrink, the capillary force of water used to rinse a photoresist mask approaches the point of being greater than adhesion force of the photoresist to the ARC. When the capillary force exceeds the adhesion force, the features of the mask may collapse because the water pulls adjacent features together as the water dries. By depositing a hermetic oxide layer over the ARC before depositing the photoresist, the adhesion force may exceed the capillary force and the features of the photoresist mask may not collapse.
摘要翻译：本发明包括当浸渍显影后干燥光致抗蚀剂掩模时减少光致抗蚀剂掩模塌陷的方法。随着特征尺寸的不断缩小，用于冲洗光致抗蚀剂掩模的水的毛细管力接近光致抗蚀剂对ARC的粘附力。当毛细管力超过粘附力时，面具的特征可能会因为水干燥而将相邻的特征拉到一起而崩溃。通过在沉积光致抗蚀剂之前在ARC上沉积气密的氧化物层，粘合力可能会超过毛细管力，并且光致抗蚀剂掩模的特征可能不会崩溃。

8. 发明授权

US07928003B2 Air gap interconnects using carbon-based films 有权
标题翻译：气隙互连使用碳基薄膜
公开(公告)号：US07928003B2
公开(公告)日：2011-04-19
申请号：US12249172
申请日：2008-10-10
申请人： Mehul Naik
发明人： Mehul Naik
IPC分类号： H01L21/00
CPC分类号： H01L21/7682 , H01L21/31144 , H01L21/76807 , H01L21/76813 , H01L21/76834 , H01L21/76837 , H01L21/76885
摘要： A method of forming an interconnect structure comprising: forming a sacrificial inter-metal dielectric (IMD) layer over a substrate, wherein the sacrificial IMD layer comprising a carbon-based film, such as amorphous carbon, advanced patterning films, porous carbon, or any combination thereof; forming a plurality of metal interconnect lines within the sacrificial IMD layer; removing the sacrificial IMD layer, with an oxygen based reactive process; and depositing a non-conformal dielectric layer to form air gaps between the plurality of metal interconnect lines. The metal interconnect lines may comprise copper, aluminum, tantalum, tungsten, titanium, tantalum nitride, titanium nitride, tungsten nitride, or any combination thereof. Carbon-based films and patterned photoresist layers may be simultaneously removed with the same reactive process. Highly reactive hydrogen radicals processes may be used to remove the carbon-based film and simultaneously pre-clean the metal interconnect lines prior to the deposition of a conformal metal barrier liner.
摘要翻译：一种形成互连结构的方法，包括：在衬底上形成牺牲金属间电介质（IMD）层，其中所述牺牲IMD层包括碳基膜，例如无定形碳，高级图案化膜，多孔碳或任何的组合在所述牺牲IMD层内形成多个金属互连线; 用氧基反应过程除去牺牲的IMD层; 以及沉积非共形绝缘层以在所述多个金属互连线之间形成气隙。金属互连线可以包括铜，铝，钽，钨，钛，氮化钽，氮化钛，氮化钨或其任何组合。可以使用相同的反应过程同时去除碳基膜和图案化的光致抗蚀剂层。可以使用高反应性氢自由基方法去除碳基膜，同时在沉积保形金属屏障衬垫之前预先清洁金属互连线。

9. 发明申请

US20080020570A1 Dual damascene fabrication with low k materials 失效
标题翻译：具有低k材料的双镶嵌制造
公开(公告)号：US20080020570A1
公开(公告)日：2008-01-24
申请号：US11488529
申请日：2006-07-18
申请人： Mehul Naik
发明人： Mehul Naik
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02118 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/31633 , H01L21/76808 , H01L21/76835
摘要： The invention provides methods and apparatuses for fabricating a dual damascene structure on a substrate. First, trench lithography and trench patterning are performed on the surface of a substrate to etch a low-k dielectric material layer to a desired etch depth to form a trench prior to forming of a via. The trenches can be filled with an organic fill material and a dielectric hard mask layer can be deposited. Then, via lithography and via resist pattering are performed. Thereafter, the dielectric hard mask and the organic fill material are sequentially etched to form vias on the surface of the substrate, where the trenches are protected by the organic fill material from being etched. A bottom etch stop layer on the bottom of the vias is then etched and the organic fill material is striped. As a result, the invention provides good patterned profiles of the via and trench openings of a dual damascene structure.
摘要翻译：本发明提供了在衬底上制造双镶嵌结构的方法和装置。首先，在衬底的表面上进行沟槽光刻和沟槽图案化以将低k电介质材料层蚀刻到期望的蚀刻深度，以在形成通孔之前形成沟槽。可以用有机填充材料填充沟槽，并且可以沉积电介质硬掩模层。然后，通过光刻和通孔抗蚀剂图案进行。此后，依次蚀刻电介质硬掩模和有机填充材料，以在衬底的表面上形成通孔，其中沟槽被有机填充材料保护而不被蚀刻。然后蚀刻通孔底部的底部蚀刻停止层，并将有机填充材料条纹化。结果，本发明提供了双镶嵌结构的通孔和沟槽开口的良好的图案轮廓。

10. 发明授权

US06458684B1 Single step process for blanket-selective CVD aluminum deposition 失效
标题翻译：毯式选择性CVD铝沉积的单步法
公开(公告)号：US06458684B1
公开(公告)日：2002-10-01
申请号：US09497390
申请日：2000-02-03
申请人： Ted Guo , Liang-Yuh Chen , Mehul Naik , Roderick C. Mosely
发明人： Ted Guo , Liang-Yuh Chen , Mehul Naik , Roderick C. Mosely
IPC分类号： H01L2144
CPC分类号： C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L21/76879
摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectic layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.
摘要翻译：本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在半微米孔径宽度应用中形成连续的无空隙触点或通孔。在本发明的一个方面中，在导电部件上形成电介质层。然后在蚀刻通过成核和电介质层的高纵横比孔之前将薄的成核层沉积到介电层上，以暴露孔底板上的下面的导电构件。然后将CVD金属层沉积到结构上以实现孔内的选择性沉积，同时优选地还在场上形成覆盖层。本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间层。

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