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1. 发明申请

US20220069772A1 CRYSTAL OSCILLATOR AND PHASE NOISE REDUCTION METHOD THEREOF 有权
公开(公告)号：US20220069772A1
公开(公告)日：2022-03-03
申请号：US17306959
申请日：2021-05-04
申请人： MEDIATEK INC.
发明人： Chien-Wei Chen , Yu-Li Hsueh , Keng-Meng Chang , Yao-Chi Wang
IPC分类号： H03B5/36 , H03K19/21
摘要： A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

2. 发明授权

US11139818B1 Fast-locking phase-locked loop and associated fast-locking method thereof 有权
公开(公告)号：US11139818B1
公开(公告)日：2021-10-05
申请号：US17124518
申请日：2020-12-17
申请人： MEDIATEK INC.
发明人： Po-Chun Huang , Yu-Li Hsueh , Chao-Ching Hung
IPC分类号： H03L7/10 , H03L7/093
摘要： A fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof are provided. The fast-locking PLL may include a gear-shifting loop filter, which is configured to have a dynamic bandwidth. The gear-shifting loop filter may include a resistor set and a capacitor set coupled to the resistor set, where the resistor set is configured to have a dynamic resistance, and the capacitor set is configured to have a dynamic capacitance. More particularly, the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.

3. 发明授权

US10483845B2 Charge pump having level-shifting mechanism 有权
公开(公告)号：US10483845B2
公开(公告)日：2019-11-19
申请号：US16137534
申请日：2018-09-20
申请人： MEDIATEK INC.
发明人： Yu-Li Hsueh , Chih-Hsien Shen , Chao-Ching Hung , Po-Chun Huang
IPC分类号： H03L7/089 , H02M3/07 , H03L7/099
摘要： The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.

4. 发明授权

US09467156B2 Frequency synthesizing module and related frequency gain determining method 有权
标题翻译：频率合成模块及相关频率增益确定方法
公开(公告)号：US09467156B2
公开(公告)日：2016-10-11
申请号：US14848348
申请日：2015-09-09
申请人： MEDIATEK INC.
发明人： Chao-Ching Hung , Yu-Li Hsueh
IPC分类号： H03L7/16 , H03L7/089 , H03L7/099
CPC分类号： H03L7/16 , H03C3/0925 , H03C3/0941 , H03C3/0958 , H03L7/0891 , H03L7/099 , H03L7/0991 , H03L7/183 , H03L2207/06
摘要： A frequency synthesizing module includes an operating circuit, for generating a control voltage according to a reference signal and a feedback signal; a controllable oscillating circuit, configured for generating an oscillating signal according to the control voltage and a first control signal, comprising a first oscillating circuit with a first frequency gain, and a second oscillating circuit with a second frequency gain; a feedback circuit, for generating the feedback signal according to the oscillating signal and a second control signal; a control circuit, for generating the first control signal and the second control signal; wherein the control circuit adjusts the first control signal by a first value and adjusts the second control signal by a second value to estimate the first frequency gain of the first oscillating circuit; wherein the first value is proportional to the second value.
摘要翻译：频率合成模块包括用于根据参考信号和反馈信号产生控制电压的操作电路; 可控振荡电路，被配置为根据所述控制电压产生振荡信号;以及第一控制信号，包括具有第一频率增益的第一振荡电路和具有第二频率增益的第二振荡电路; 反馈电路，用于根据振荡信号和第二控制信号产生反馈信号; 用于产生第一控制信号和第二控制信号的控制电路; 其中所述控制电路将所述第一控制信号调整为第一值，并且将所述第二控制信号调整为第二值以估计所述第一振荡电路的第一频率增益; 其中所述第一值与所述第二值成正比。

5. 发明授权

US09160353B2 Phase frequency detector and charge pump for phase lock loop fast-locking 有权
标题翻译：相位频率检测器和电荷泵用于锁相环快速锁定
公开(公告)号：US09160353B2
公开(公告)日：2015-10-13
申请号：US14158657
申请日：2014-01-17
申请人： Mediatek Inc.
发明人： Yu-Li Hsueh , Jing-Hong Conan Zhan
IPC分类号： H03L7/10 , H03L7/089 , H03L7/107
CPC分类号： H03L7/10 , H03L7/0891 , H03L7/0896 , H03L7/1072
摘要： The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.
摘要翻译：本发明提供了一种解决方案，通过各种电路配置通过各种电路配置升级相位频率检测器（PFD）和电荷泵（CP）增益，提供令人满意的性能，而不需要锁相环（PLL）电路的显着占地面积，采用一个或多个触发器，延迟元件和高级电路技术。

6. 发明授权

US08766684B2 Charge pump, phase frequency detector and charge pump methods 有权
标题翻译：电荷泵，相频检测器和电荷泵方法
公开(公告)号：US08766684B2
公开(公告)日：2014-07-01
申请号：US13769810
申请日：2013-02-18
申请人： Mediatek Inc.
发明人： Yu-Li Hsueh , Yi-Hsien Cho , Jing-Hong Conan Zhan
IPC分类号： H03L7/06
CPC分类号： H03L5/00 , H03L7/089 , H03L7/0895 , H03L7/0896 , H03L7/093
摘要： A phase/frequency detector for controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase.
摘要翻译：用于控制电荷泵的相位/频率检测器包括：核心电路，被布置成根据参考时钟信号和输入时钟信号之间的相位/频率差输出第一相位信号和第二相位信号; 以及定时电路，其耦合到所述核心电路并被布置成根据所述第一相位信号和所述第二相位信号产生用于控制所述电荷泵的第一控制信号和第二控制信号，其中，所述第一控制信号和所述第二控制信号中的仅一个当参考时钟信号和输入时钟信号在相位上基本上相同时，控制信号指示使能操作。

7. 发明授权

US11183971B2 Method for startup of crystal oscillator with aid of external clock injection, associated crystal oscillator and monitoring circuit therein 有权
公开(公告)号：US11183971B2
公开(公告)日：2021-11-23
申请号：US17026275
申请日：2020-09-20
申请人： MEDIATEK INC.
发明人： Chien-Wei Chen , Yu-Li Hsueh , Po-Chun Huang
IPC分类号： H03B5/06 , G01R25/00 , H03B5/36 , H03B5/32
摘要： A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.

8. 发明授权

US10809757B2 Clock buffer having low power, low noise and low spur 有权
公开(公告)号：US10809757B2
公开(公告)日：2020-10-20
申请号：US16553163
申请日：2019-08-27
申请人： MEDIATEK INC.
发明人： Chien-Wei Chen , Yu-Li Hsueh
IPC分类号： H03K19/096 , G06F1/06 , H03K17/687 , H03K19/20
摘要： The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

9. 发明申请

US20190207640A1 WIRELESS SYSTEM HAVING LOCAL OSCILLATOR SIGNAL DERIVED FROM REFERENCE CLOCK OUTPUT OF ACTIVE OSCILLATOR THAT HAS NO ELECTROMECHANICAL RESONATOR 审中-公开
公开(公告)号：US20190207640A1
公开(公告)日：2019-07-04
申请号：US16152391
申请日：2018-10-04
申请人： MEDIATEK INC.
发明人： Jui-Lin Hsu , Chao-Ching Hung , Tzu-Chin Lin , Wei-Hsiu Hsu , Yu-Li Hsueh , Jing-Hong Conan Zhan , Chih-Ming Hung
IPC分类号： H04B1/403 , H03B5/12 , G01S7/03
CPC分类号： H04B1/403 , G01S7/03 , G01S7/032 , H03B5/12 , H03B2200/008 , H03K5/135 , H04B7/2662
摘要： A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.

10. 发明授权

US10020777B2 Voltage controlled oscillator and control method thereof 有权
公开(公告)号：US10020777B2
公开(公告)日：2018-07-10
申请号：US15239818
申请日：2016-08-17
申请人： MEDIATEK INC.
发明人： Chao-Ching Hung , Po-Chun Huang , Yu-Li Hsueh
IPC分类号： H03B5/08 , H03B5/12 , H03B5/06 , H03L5/00 , H03L7/099 , H03B5/10 , H03B1/00
CPC分类号： H03B5/1234 , H03B1/00 , H03B5/06 , H03B5/10 , H03B5/1212 , H03B5/1215 , H03B2200/0094 , H03L5/00 , H03L7/099
摘要： A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.

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