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1. 发明申请

US20060199328A1 Non-dispersive high density polysilicon capacitor utilizing amorphous silicon electrodes 审中-公开
标题翻译：非分散高密度多晶硅电容器利用非晶硅电极
公开(公告)号：US20060199328A1
公开(公告)日：2006-09-07
申请号：US11072186
申请日：2005-03-04
申请人： Maxwell Lippitt , Byron Williams , Michael DuBois , Betty Mercer , Scott Montgomery , C. Matthew Thompson , Evelyn Lafferty
发明人： Maxwell Lippitt , Byron Williams , Michael DuBois , Betty Mercer , Scott Montgomery , C. Matthew Thompson , Evelyn Lafferty
IPC分类号： H01L21/8232
CPC分类号： H01L27/0629 , H01L28/60
摘要： The present invention provides, in one aspect, a method of fabricating a capacitor 615, comprising forming a first electrode 610, placing a dielectric 515 over the first electrode, and locating a second electrode 510 over the dielectric wherein at least one of the first or second electrodes 610, 510 is doped amorphous silicon.
摘要翻译：本发明在一个方面提供一种制造电容器615的方法，包括形成第一电极610，将电介质515放置在第一电极上方，并将第二电极510定位在电介质上，其中第一或第第二电极610,510是掺杂的非晶硅。

2. 发明申请

US20070075348A1 High density, high Q capacitor on top of a protective layer 审中-公开
标题翻译：高密度，高Q电容器在保护层顶部
公开(公告)号：US20070075348A1
公开(公告)日：2007-04-05
申请号：US11239244
申请日：2005-09-30
申请人： Byron Williams , Maxwell Lippitt , Darius Crenshaw , Laurinda Ng , Betty Mercer , Scott Montgomery , C. Thompson
发明人： Byron Williams , Maxwell Lippitt , Darius Crenshaw , Laurinda Ng , Betty Mercer , Scott Montgomery , C. Thompson
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the invention, there are methods for making and there is an integrated circuit comprising a semiconductor substrate comprising device elements and a metallization layer interconnecting the device elements and having an uppermost layer. The integrated circuit can also include a protective overcoat formed over the metallization layer, the protective overcoat having a plurality of patterned regions that expose portions of the metallization layer, a first conductive layer formed on the protective overcoat, and a dielectric layer formed over the first conductive layer. The integrated circuit can further include a second conductive layer formed over the dielectric layer and a plurality of sidewall spacers contacting end portions of the first conductive layer.
摘要翻译：根据本发明，存在制造方法，并且存在包括半导体衬底的集成电路，该半导体衬底包括器件元件和互连器件元件并具有最上层的金属化层。集成电路还可以包括形成在金属化层上的保护外涂层，保护外涂层具有暴露金属化层的部分的多个图案化区域，形成在保护外涂层上的第一导电层，以及形成在第一导电层。集成电路还可以包括形成在电介质层上的第二导电层和与第一导电层的端部接触的多个侧壁间隔件。

3. 发明申请

US20050239277A1 Interconnect and a method of manufacture therefor 有权
标题翻译：互连及其制造方法
公开(公告)号：US20050239277A1
公开(公告)日：2005-10-27
申请号：US10828592
申请日：2004-04-21
申请人： Betty Mercer , Erika Shoemaker , Byron Williams , Laurinda Ng , Alec Morton , C. Thompson
发明人： Betty Mercer , Erika Shoemaker , Byron Williams , Laurinda Ng , Alec Morton , C. Thompson
IPC分类号： G03C1/85 , H01L21/44 , H01L21/60
CPC分类号： H01L24/11 , H01L2224/039 , H01L2224/03912 , H01L2224/0401 , H01L2224/05005 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/0518 , H01L2224/05184 , H01L2224/05572 , H01L2224/05647 , H01L2224/1147 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (100), among other elements, includes a surface conductive lead (160) located in an opening formed within a protective overcoat (110), and a barrier layer (140) located between the protective overcoat (110) and the surface conductive lead (160), a portion of the barrier layer (140) forming a skirt (145) that extends outside a footprint of the surface conductive lead (160).
摘要翻译：本发明提供了一种用于集成电路的互连，一种用于制造该互连的方法，以及一种用于制造包括该互连的集成电路的方法。除了其它元件之外，互连（100）包括位于形成在保护外涂层（110）内的开口中的表面导电引线（160）和位于保护外涂层（110）和表面导电导线（160），阻挡层（140）的形成裙部（145）的部分延伸到表面导电引线（160）的覆盖区外部。

4. 发明授权

US07902033B2 Methods and devices for a high-k stacked capacitor 有权
标题翻译：高k堆叠电容器的方法和装置
公开(公告)号：US07902033B2
公开(公告)日：2011-03-08
申请号：US12029798
申请日：2008-02-12
申请人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
发明人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
IPC分类号： H01L21/20
CPC分类号： H01L28/91
摘要： An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.
摘要翻译：实施例通常涉及形成电容器的方法。该方法包括在集成电路的保护外涂层或后端电介质层内形成多个孔，并沉积多层金属，每层金属电连接到相关电极。该方法还包括交替地在多层金属之间沉积多层电介质，并将多层金属的底层耦合到集成电路的顶层金属层中的接触节点。

5. 发明申请

US20050127516A1 Small viatops for thick copper connectors 审中-公开
标题翻译：用于厚铜连接器的小型变电极
公开(公告)号：US20050127516A1
公开(公告)日：2005-06-16
申请号：US10735374
申请日：2003-12-12
申请人： Betty Mercer , Alec Morton , Byron Williams , Laurinda Ng , C. Thompson , Der-E Jan , Sunny Lee , Phuong-Lan Thi Tran
发明人： Betty Mercer , Alec Morton , Byron Williams , Laurinda Ng , C. Thompson , Der-E Jan , Sunny Lee , Phuong-Lan Thi Tran
IPC分类号： H01L21/44 , H01L21/768 , H01L29/40
CPC分类号： H01L21/76877 , H01L21/76838
摘要： The present invention relates to integrated circuits comprising a protective overcoat and thick copper connectors. According to one aspect of the inventions, vias in the protective overcoat are substantially filled with tungsten plugs, or plugs of another metal with a relatively low coefficient of thermal expansion. According to another aspect of the invention, large vias in the protective overcoat are replaced with arrays of smaller vias. The invention reduces the likelihood of device failures during temperature cycling tests. Also, the invention allows for smaller vias in the protective overcoat and removal of interconnect functions to the thick copper layer.
摘要翻译：本发明涉及包括保护外涂层和厚铜连接器的集成电路。根据本发明的一个方面，保护性外涂层中的通孔基本上填充有钨塞或具有相对低的热膨胀系数的另一种金属的塞子。根据本发明的另一方面，保护性外涂层中的大的通孔被更小的通孔的阵列所取代。本发明降低了温度循环测试期间设备故障的可能性。此外，本发明允许保护性外涂层中的较小的通孔和去除厚铜层的互连功能。

6. 发明授权

US08497565B2 Multiple electrode layer backend stacked capacitor 有权
标题翻译：多电极层后端层叠电容器
公开(公告)号：US08497565B2
公开(公告)日：2013-07-30
申请号：US13043066
申请日：2011-03-08
申请人： Byron Lovell Willaims , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
发明人： Byron Lovell Willaims , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
IPC分类号： H01L21/02
CPC分类号： H01L28/91
摘要： In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115). The sidewalls of the top and middle electrode vias (165A, 165B) are lined with insulating material to electrically isolate the metal electrode layer ends.
摘要翻译：在公开的实施例中，叠层电容器（100）具有与保护性地设置在保护孔（140A，140B，140C）内的电介质层（142A，142B）交错的底部，中间和顶部金属电极层（141A，141B，141C）外部涂层或后端电介质层（110）覆盖在集成电路（105）的顶部金属层（115）上。顶部电极（155）接触顶部金属电极层（141C）。底部电极（150）通过（165A）将顶部金属电极层（141C）的隔离部分电耦合到顶部金属层（115）中与第一接触节点（135A）接触的第一接触节点（135A）底部金属电极层（141A）。中间电极（160）将未被顶部金属层（115）覆盖的中间金属电极层（141B）的一部分通过中间电极（165B）电耦合到顶部金属电极中的第二接触节点（135B）层（115）。顶部和中间电极通孔（165A，165B）的侧壁衬有绝缘材料以电绝缘金属电极层端部。

7. 发明申请

US20110156209A1 MULTIPLE ELECTRODE LAYER BACKEND STACKED CAPACITOR 有权
标题翻译：多层电极层背板堆叠电容
公开(公告)号：US20110156209A1
公开(公告)日：2011-06-30
申请号：US13043066
申请日：2011-03-08
申请人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
发明人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
IPC分类号： H01L29/92
CPC分类号： H01L28/91
摘要： In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115). The sidewalls of the top and middle electrode vias (165A, 165B) are lined with insulating material to electrically isolate the metal electrode layer ends.
摘要翻译：在公开的实施例中，叠层电容器（100）具有与保护性地设置在保护孔（140A，140B，140C）内的电介质层（142A，142B）交错的底部，中间和顶部金属电极层（141A，141B，141C）外部涂层或后端电介质层（110）覆盖在集成电路（105）的顶部金属层（115）上。顶部电极（155）接触顶部金属电极层（141C）。底部电极（150）通过（165A）将顶部金属电极层（141C）的隔离部分电耦合到顶部金属层（115）中与第一接触节点（135A）接触的第一接触节点（135A）底部金属电极层（141A）。中间电极（160）将未被顶部金属层（115）覆盖的中间金属电极层（141B）的一部分通过中间电极（165B）电耦合到顶部金属电极中的第二接触节点（135B）层（115）。顶部和中间电极通孔（165A，165B）的侧壁衬有绝缘材料以电绝缘金属电极层端部。

8. 发明申请

US20090200637A1 METHODS AND DEVICES FOR A HIGH-K STACKED CAPACITOR 有权
标题翻译：用于高K堆叠电容器的方法和装置
公开(公告)号：US20090200637A1
公开(公告)日：2009-08-13
申请号：US12029798
申请日：2008-02-12
申请人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
发明人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/91
摘要： An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.
摘要翻译：实施例通常涉及形成电容器的方法。该方法包括在集成电路的保护外涂层或后端电介质层内形成多个孔，并沉积多层金属，每层金属电连接到相关电极。该方法还包括交替地在多层金属之间沉积多层电介质，并将多层金属的底层耦合到集成电路的顶层金属层中的接触节点。

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