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1. 发明申请

US20130056874A1 Protection of intermetal dielectric layers in multilevel wiring structures 审中-公开
标题翻译：多层布线结构中金属间电介质层的保护
公开(公告)号：US20130056874A1
公开(公告)日：2013-03-07
申请号：US13226281
申请日：2011-09-06
申请人： Maxime Darnon , Geraud J.-M. Dubois , Sebastian U. Engelmann , Teddie P. Magbitang , Sampath Purushothaman , Muthumanickam Sankarapandian , Willi Volksen
发明人： Maxime Darnon , Geraud J.-M. Dubois , Sebastian U. Engelmann , Teddie P. Magbitang , Sampath Purushothaman , Muthumanickam Sankarapandian , Willi Volksen
IPC分类号： H01L21/3065 , H01L23/48
CPC分类号： H01L21/3105 , H01L21/02203 , H01L21/31116 , H01L21/76808 , H01L21/76814 , H01L21/76826
摘要： A semiconductor device is accepted at a stage of its fabrication, at which stage the device includes a diffusion-barrier cap-material (DBCM) layer and an intermetal dielectric layer covering the DBCM layer. The DBCM layer is exposed and it is suitable for removal by an etching procedure in a portion of a pattern contained in the intermetal dielectric layer. A silylation treatment is performed on the semiconductor device prior to the etching procedure for removing the DBCM layer. The intermetal dielectric layer of the completed device has surfaces in contact with metal interconnects and metal vias, and it may have an excess of carbon content near at least a portion of the these surfaces.
摘要翻译：半导体器件在其制造阶段被接受，在该阶段，器件包括覆盖DBCM层的扩散阻挡帽 - 材料（DBCM）层和金属间电介质层。 DBCM层被暴露，并且适合于在金属间电介质层中包含的图案的一部分中通过蚀刻工艺去除。在用于去除DBCM层的蚀刻过程之前，在半导体器件上进行甲硅烷基化处理。完成的器件的金属间电介质层具有与金属互连和金属通孔接触的表面，并且其可以在这些表面的至少一部分附近具有过量的碳含量。

2. 发明申请

US20130087860A1 BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS 有权
标题翻译：无边界自对准的金属接触方式使用可印制的电介质材料
公开(公告)号：US20130087860A1
公开(公告)日：2013-04-11
申请号：US13270047
申请日：2011-10-10
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
IPC分类号： H01L27/092 , H01L21/283
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
摘要翻译：无边界自对准金属接触高密度互补金属氧化物半导体（CMOS）电路及其构造方法。示例性方法包括为相邻晶体管的栅极形成的用于金属沉积的封闭区域和邻近相邻晶体管的源极区域和漏极区域的相对的一对电介质壁。该方法还包括在封闭区域内沉积金属层。这样形成的金属触点与封闭区域自对准。

3. 发明授权

US08916054B2 High fidelity patterning employing a fluorohydrocarbon-containing polymer 有权
标题翻译：采用含氟代烃基聚合物的高保真图案
公开(公告)号：US08916054B2
公开(公告)日：2014-12-23
申请号：US13281749
申请日：2011-10-26
申请人： Markus Brink , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Hiroyuki Miyazoe , Masahiro Nakamura
发明人： Markus Brink , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Hiroyuki Miyazoe , Masahiro Nakamura
IPC分类号： B44C1/22 , H01L21/033 , H01L21/311 , G03F7/40 , G03F7/09
CPC分类号： G03F7/094 , G03F7/091 , G03F7/40 , H01L21/0332 , H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/31144 , Y10T428/24479
摘要： A stack of a hard mask layer, a soft mask layer, and a photoresist is formed on a substrate. The photoresist is patterned to include at least one opening. The pattern is transferred into the soft mask layer by an anisotropic etch, which forms a carbon-rich polymer that includes more carbon than fluorine. The carbon-rich polymer can be formed by employing a fluorohydrocarbon-containing plasma generated with fluorohydrocarbon molecules including more hydrogen than fluorine. The carbon-rich polymer coats the sidewalls of the soft mask layer, and prevents widening of the pattern transferred into the soft mask. The photoresist is subsequently removed, and the pattern in the soft mask layer is transferred into the hard mask layer. Sidewalls of the hard mask layer are coated with the carbon-rich polymer to prevent widening of the pattern transferred into the hard mask.
摘要翻译：在基板上形成硬掩模层，软掩模层和光致抗蚀剂的堆叠。图案化光致抗蚀剂以包括至少一个开口。该图案通过各向异性蚀刻转移到软掩模层中，其形成包含比氟更多的碳的富碳聚合物。富含碳的聚合物可以通过使用包含比氟更多的氢的氟代烃分子产生的含氟代烃等离子体形成。富含碳的聚合物涂覆软掩模层的侧壁，并且防止转移到软掩模中的图案的加宽。随后去除光致抗蚀剂，并将软掩模层中的图案转移到硬掩模层中。用富含碳的聚合物涂覆硬掩模层的侧壁以防止转移到硬掩模中的图案变宽。

4. 发明授权

US08298881B2 Nanowire FET with trapezoid gate structure 有权
标题翻译：具有梯形栅极结构的纳米线FET
公开(公告)号：US08298881B2
公开(公告)日：2012-10-30
申请号：US12824293
申请日：2010-06-28
申请人： Jeffrey W. Sleight , Sarunya Bangsaruntip , Sebastian U. Engelmann , Ying Zhang
发明人： Jeffrey W. Sleight , Sarunya Bangsaruntip , Sebastian U. Engelmann , Ying Zhang
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/4232 , H01L29/513 , H01L29/66439
摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
摘要翻译：在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源区和漏区。

5. 发明授权

US09190316B2 Low energy etch process for nitrogen-containing dielectric layer 有权
标题翻译：含氮介电层的低能蚀刻工艺
公开(公告)号：US09190316B2
公开(公告)日：2015-11-17
申请号：US13281732
申请日：2011-10-26
申请人： Markus Brink , Robert L. Bruce , Sebastian U. Engelmann , Nicholas C. M. Fuller , Hiroyuki Miyazoe , Masahiro Nakamura
发明人： Markus Brink , Robert L. Bruce , Sebastian U. Engelmann , Nicholas C. M. Fuller , Hiroyuki Miyazoe , Masahiro Nakamura
IPC分类号： H01L21/00 , H01L21/768 , H01L21/311 , H01L21/321
CPC分类号： H01L23/53295 , H01L21/31116 , H01L21/31144 , H01L21/3212 , H01L21/76802 , H01L21/76813 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.
摘要翻译：在基板上形成从底部到顶部包括含氮介电层，互连层介电材料层和硬掩模层的堆叠。通过蚀刻对硬掩模层和互连层电介质材料层进行图案化。使用图案化的硬掩模层作为蚀刻掩模，通过使用含氟烃的等离子体穿过含氮介电层的穿透各向异性蚀刻来对含氮介电层进行图案化。用于产生含氟烃的等离子体的氟烃气体产生富含碳的聚合物残余物，其与含氮介电层相互作用以形成挥发性化合物。等离子体能量可以降低到低于100eV，以减少互连层介电材料层的物理暴露表面的损伤。

6. 发明授权

US08765613B2 High selectivity nitride etch process 有权
标题翻译：高选择性氮化物蚀刻工艺
公开(公告)号：US08765613B2
公开(公告)日：2014-07-01
申请号：US13281688
申请日：2011-10-26
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Masahiro Nakamura
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Masahiro Nakamura
IPC分类号： H01L21/302
CPC分类号： H01L29/6653 , H01L21/31116 , H01L21/76802 , H01L21/76897 , H01L29/6656 , H01L29/6659
摘要： An anisotropic silicon nitride etch provides selectivity to silicon and silicon oxide by forming a fluorohydrocarbon-containing polymer on silicon surfaces and silicon oxide surfaces. Selective fluorohydrocarbon deposition is employed to provide selectivity to non-nitride surfaces. The fluorohydrocarbon-containing polymer interacts with silicon nitride to form a volatile compound, thereby enabling etching of silicon nitride. The fluorohydrocarbon-containing polymer interacts with silicon oxide at a low reaction rate, retarding, or completely stopping, the etching of silicon oxide. The fluorohydrocarbon-containing polymer does not interact with silicon, and protects silicon from the plasma. The anisotropic silicon nitride etch can be employed to etch silicon nitride selective to silicon and silicon oxide in any dimension, including small dimensions less than 50 nm.
摘要翻译：各向异性氮化硅蚀刻通过在硅表面和氧化硅表面上形成含氟代烃的聚合物来提供对硅和氧化硅的选择性。使用选择性氟代烃沉积来提供对非氮化物表面的选择性。含氟烃聚合物与氮化硅相互作用以形成挥发性化合物，从而能够蚀刻氮化硅。含氟烃聚合物以低反应速率与氧化硅相互作用，阻止或完全停止氧化硅的蚀刻。含氟烃聚合物不与硅相互作用，并保护硅免受等离子体的影响。可以采用各向异性氮化硅蚀刻来蚀刻任选尺寸的硅和氧化硅的氮化硅，包括小于50nm的小尺寸。

7. 发明申请

US20130105996A1 LOW ENERGY ETCH PROCESS FOR NITROGEN-CONTAINING DIELECTRIC LAYER 有权
标题翻译：含氮电介质层的低能量蚀刻工艺
公开(公告)号：US20130105996A1
公开(公告)日：2013-05-02
申请号：US13281732
申请日：2011-10-26
申请人： Markus Brink , Robert L. Bruce , Sebastian U. Engelmann , Nicholas C. M. Fuller , Hiroyuki Miyazoe , Masahiro Nakamura
发明人： Markus Brink , Robert L. Bruce , Sebastian U. Engelmann , Nicholas C. M. Fuller , Hiroyuki Miyazoe , Masahiro Nakamura
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/31116 , H01L21/31144 , H01L21/3212 , H01L21/76802 , H01L21/76813 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.
摘要翻译：在基板上形成从底部到顶部包括含氮介电层，互连层介电材料层和硬掩模层的堆叠。通过蚀刻对硬掩模层和互连层电介质材料层进行图案化。使用图案化的硬掩模层作为蚀刻掩模，通过使用含氟烃的等离子体穿过含氮介电层的穿透各向异性蚀刻来对含氮介电层进行图案化。用于产生含氟烃的等离子体的氟烃气体产生富含碳的聚合物残余物，其与含氮介电层相互作用以形成挥发性化合物。等离子体能量可以降低到低于100eV，以减少互连层介电材料层的物理暴露表面的损伤。

8. 发明申请

US20130087882A1 LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION 有权
公开(公告)号：US20130087882A1
公开(公告)日：2013-04-11
申请号：US13269552
申请日：2011-10-07
申请人： Josephine B. Chang , Leland Chang , Sebastian U. Engelmann , Michael A. Guillorn
发明人： Josephine B. Chang , Leland Chang , Sebastian U. Engelmann , Michael A. Guillorn
IPC分类号： H01L27/12 , H01L21/56
CPC分类号： B81C1/0023 , B81B2207/015 , B81C1/00801 , B81C2203/0714 , B81C2203/0742 , H01L21/565 , H01L21/845 , H01L27/1211 , H01L2924/0002 , H01L2924/00
摘要： Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

9. 发明申请

US20100252810A1 GATE PATTERNING OF NANO-CHANNEL DEVICES 有权
标题翻译： NANO通道设备的门控方案
公开(公告)号：US20100252810A1
公开(公告)日：2010-10-07
申请号：US12417954
申请日：2009-04-03
申请人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L29/41 , H01L21/306 , H01L21/302
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译：提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。在另一个实施例中，使用封装/钝化层。在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

10. 发明授权

US08829625B2 Nanowire FET with trapezoid gate structure 有权
标题翻译：具有梯形栅极结构的纳米线FET
公开(公告)号：US08829625B2
公开(公告)日：2014-09-09
申请号：US13572114
申请日：2012-08-10
申请人： Jeffrey W. Sleight , Sarunya Bangsaruntip , Sebastian U. Engelmann , Ying Zhang
发明人： Jeffrey W. Sleight , Sarunya Bangsaruntip , Sebastian U. Engelmann , Ying Zhang
IPC分类号： H01L27/088
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/4232 , H01L29/513 , H01L29/66439
摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
摘要翻译：在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源极和漏极区域。

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