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1. 发明申请

US20140203175A1 OPTICAL I/O SYSTEM USING PLANAR LIGHT-WAVE INTEGRATED CIRCUIT 有权
标题翻译：使用平面光波集成电路的光学I / O系统
公开(公告)号：US20140203175A1
公开(公告)日：2014-07-24
申请号：US13996531
申请日：2011-12-30
申请人： Mauro J. Kobrinsky , Henning Braunisch , Shawna M. Liff , Peter L. Chang , Bruce A. Block , Johanna M. Swan
发明人： Mauro J. Kobrinsky , Henning Braunisch , Shawna M. Liff , Peter L. Chang , Bruce A. Block , Johanna M. Swan
IPC分类号： H04B10/25 , G02B6/12
CPC分类号： G02B6/12004 , G02B6/12 , G02B6/30 , G02B6/4214 , G02B6/4257 , G02B6/428 , G02B2006/12061 , G02B2006/12121 , G02B2006/12123 , H01L21/563 , H01L23/49827 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/167 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/81011 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83048 , H01L2224/83102 , H01L2224/83986 , H01L2224/92125 , H01L2924/12042 , H01L2924/12043 , H01L2924/1431 , H01L2924/1432 , H01L2924/15311 , H01L2924/15312 , H04B10/25 , H04B10/40 , H04B10/801 , H01L2924/00014 , H01L2924/014
摘要： Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
摘要翻译：光子元件放置在处理器封装上，使光信号靠近处理器管芯。处理器封装包括处理器管芯耦合到其上的基板，并且允许处理器管芯连接到印刷电路板。处理器封装还包括收发器逻辑，电光转换电路和光耦合器。电光转换电路可以包括激光器，调制器和用于发射和接收光信号的光电检测器。耦合器连接到从处理器封装延伸的光纤。多个光纤可以被带到处理器封装，允许与处理器的可扩展的高速，高带宽互连。

2. 发明授权

US09507086B2 Optical I/O system using planar light-wave integrated circuit 有权
标题翻译：光I / O系统采用平面光波集成电路
公开(公告)号：US09507086B2
公开(公告)日：2016-11-29
申请号：US13996531
申请日：2011-12-30
申请人： Mauro J. Kobrinsky , Henning Braunisch , Shawna M. Liff , Peter L. Chang , Bruce A. Block , Johanna M. Swan
发明人： Mauro J. Kobrinsky , Henning Braunisch , Shawna M. Liff , Peter L. Chang , Bruce A. Block , Johanna M. Swan
IPC分类号： H04B10/25 , G02B6/12 , G02B6/42 , G02B6/30
CPC分类号： G02B6/12004 , G02B6/12 , G02B6/30 , G02B6/4214 , G02B6/4257 , G02B6/428 , G02B2006/12061 , G02B2006/12121 , G02B2006/12123 , H01L21/563 , H01L23/49827 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/167 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/81011 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83048 , H01L2224/83102 , H01L2224/83986 , H01L2224/92125 , H01L2924/12042 , H01L2924/12043 , H01L2924/1431 , H01L2924/1432 , H01L2924/15311 , H01L2924/15312 , H04B10/25 , H04B10/40 , H04B10/801 , H01L2924/00014 , H01L2924/014
摘要： Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
摘要翻译：光子元件放置在处理器封装上，使光信号靠近处理器管芯。处理器封装包括处理器管芯耦合到其上的基板，并且允许处理器管芯连接到印刷电路板。处理器封装还包括收发器逻辑，电光转换电路和光耦合器。电光转换电路可以包括激光器，调制器和用于发射和接收光信号的光电检测器。耦合器连接到从处理器封装延伸的光纤。多个光纤可以被带到处理器封装，允许与处理器的可扩展的高速，高带宽互连。

3. 发明授权

US09310553B2 Optical connection techniques and configurations 有权
公开(公告)号：US09310553B2
公开(公告)日：2016-04-12
申请号：US13995136
申请日：2011-11-16
申请人： Henning Braunisch , Shawna M. Liff , Peter L. Chang
发明人： Henning Braunisch , Shawna M. Liff , Peter L. Chang
IPC分类号： G02B6/12 , G02B6/42 , G02B6/46
CPC分类号： G02B6/4261 , G02B6/12 , G02B6/4201 , G02B6/4239 , G02B6/4246 , G02B6/4256 , G02B6/4257 , G02B6/4269 , G02B6/4278 , G02B6/4292 , G02B6/46 , Y10T29/49128
摘要： Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for mounting on a surface of a package substrate, the receptacle having a pluggable surface to receive an optical coupler plug such that the optical coupler plug is optically aligned with one or more optical apertures of an optoelectronic assembly that is configured to emit and/or receive light using the one or more optical apertures in a direction that is substantially perpendicular to the surface of the package substrate when the optoelectronic assembly is affixed to the package substrate. Other embodiments may be described and/or claimed.

4. 发明申请

US20130272649A1 OPTICAL CONNECTION TECHNIQUES AND CONFIGURATIONS 有权
标题翻译：光学连接技术和配置
公开(公告)号：US20130272649A1
公开(公告)日：2013-10-17
申请号：US13995136
申请日：2011-11-16
申请人： Henning Braunisch , Shawna M. Liff , Peter L. Chang
发明人： Henning Braunisch , Shawna M. Liff , Peter L. Chang
IPC分类号： G02B6/12 , G02B6/46
CPC分类号： G02B6/4261 , G02B6/12 , G02B6/4201 , G02B6/4239 , G02B6/4246 , G02B6/4256 , G02B6/4257 , G02B6/4269 , G02B6/4278 , G02B6/4292 , G02B6/46 , Y10T29/49128
摘要： Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for mounting on a surface of a package substrate, the receptacle having a pluggable surface to receive an optical coupler plug such that the optical coupler plug is optically aligned with one or more optical apertures of an optoelectronic assembly that is configured to emit and/or receive light using the one or more optical apertures in a direction that is substantially perpendicular to the surface of the package substrate when the optoelectronic assembly is affixed to the package substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供光学连接技术和配置。在一个实施例中，一种装置包括用于安装在封装基板的表面上的插座，该插座具有可插接表面以接收光耦合器插头，使得光耦合器插头与光电组件的一个或多个光学孔径光学对准其被配置为当所述光电组件固定到所述封装衬底时，使用所述一个或多个光学孔在基本上垂直于所述封装衬底的表面的方向上发射和/或接收光。可以描述和/或要求保护其他实施例。

5. 发明申请

US20140314111A1 THERMAL MANAGEMENT IN PACKAGED VCSELS 有权
标题翻译：包装VCSELS中的热管理
公开(公告)号：US20140314111A1
公开(公告)日：2014-10-23
申请号：US13698453
申请日：2011-11-18
申请人： Feras Eid , Shawna M. Liff , Henning Braunisch
发明人： Feras Eid , Shawna M. Liff , Henning Braunisch
IPC分类号： H01S5/024
CPC分类号： H01S5/02476 , H01S5/02236 , H01S5/183 , H01S5/423
摘要： Heat management systems for vertical cavity surface emitting laser (VCSEL) chips are provided. Embodiments of the invention provide substrates having, a vertical cavity surface emitting laser chip disposed on the substrate surface and electrically interconnected with the substrate, a thermal frame disposed on the substrate surface and proximate to at least three sides of the vertical cavity surface emitting laser chip, and a thermal interface material disposed between the at least three sides of the vertical cavity surface emitting laser chip and the thermal frame. The substrate can also include a transceiver chip that is operably coupled to a further integrated circuit chip and that is capable of driving the VCSEL chip.
摘要翻译：提供了垂直腔表面发射激光（VCSEL）芯片的热管理系统。本发明的实施例提供了具有设置在衬底表面上并与衬底电互连的垂直腔表面发射激光器芯片的衬底，设置在衬底表面上并且靠近垂直腔表面发射激光器芯片的至少三个侧面的热框架以及设置在垂直腔表面发射激光芯片和热框架的至少三个侧面之间的热界面材料。衬底还可以包括可操作地耦合到另一集成电路芯片并且能够驱动VCSEL芯片的收发器芯片。

6. 发明授权

US09391427B2 Thermal management in packaged VCSELs 有权
标题翻译：封装VCSEL中的热管理
公开(公告)号：US09391427B2
公开(公告)日：2016-07-12
申请号：US13698453
申请日：2011-11-18
申请人： Feras Eid , Shawna M. Liff , Henning Braunisch
发明人： Feras Eid , Shawna M. Liff , Henning Braunisch
IPC分类号： H01S5/024 , H01S5/022 , H01S5/183 , H01S5/42
CPC分类号： H01S5/02476 , H01S5/02236 , H01S5/183 , H01S5/423
摘要： Heat management systems for vertical cavity surface emitting laser (VCSEL) chips are provided. Embodiments of the invention provide substrates having a vertical cavity surface emitting laser chip disposed on the substrate surface and electrically interconnected with the substrate, a thermal frame disposed on the substrate surface and proximate to at least three sides of the vertical cavity surface emitting laser chip, and a thermal interface material disposed between the at least three sides of the vertical cavity surface emitting laser chip and the thermal frame. The substrate can also include a transceiver chip that is operably coupled to a further integrated circuit chip and that is capable of driving the VCSEL chip.
摘要翻译：提供了垂直腔表面发射激光（VCSEL）芯片的热管理系统。本发明的实施例提供了具有设置在衬底表面上并与衬底电互连的垂直腔表面发射激光器芯片的衬底，设置在衬底表面上并且靠近垂直腔表面发射激光器芯片的至少三个侧面的热框架，以及设置在垂直腔表面发射激光芯片和热框架的至少三个侧面之间的热界面材料。衬底还可以包括可操作地耦合到另一集成电路芯片并且能够驱动VCSEL芯片的收发器芯片。

7. 发明申请

US20100327424A1 Multi-chip package and method of providing die-to-die interconnects in same 有权
标题翻译：多芯片封装和提供芯片间裸片互连的方法
公开(公告)号：US20100327424A1
公开(公告)日：2010-12-30
申请号：US12459007
申请日：2009-06-24
申请人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Hinmeng Au , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
发明人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Hinmeng Au , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
IPC分类号： H01L23/538 , H01L21/60
CPC分类号： H01L23/5385 , H01L21/6835 , H01L23/13 , H01L24/14 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32245 , H01L2224/45099 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73253 , H01L2224/81001 , H01L2224/81005 , H01L2224/81801 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12042 , H01L2924/1461 , H01L2924/15153 , H01L2924/19107 , H01L2924/351 , H01L2924/00
摘要： A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
摘要翻译：多芯片封装包括具有第一侧面（111），相对的第二侧面（112）和从第一侧向第二侧延伸的第三侧面（213）的基板（110），第一模具（120））和附接到所述基板的第一侧的第二模具（130），以及邻近所述基板的第三侧并连接到所述第一模具和所述第二模具的桥接件（140）。基板的任何部分都不在桥下。该桥在第一管芯和第二管芯之间形成连接。或者，桥可以设置在衬底中的空腔（615,915）中，或者设置在衬底和裸片层（750）之间。该桥可以构成一个有源管芯，并且可以使用引线键连接到衬底（241,841,1141,1541）。

8. 发明申请

US20120261838A1 MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME 审中-公开
标题翻译：多芯片封装及其相互之间提供DIE-TO-DIE互连的方法
公开(公告)号：US20120261838A1
公开(公告)日：2012-10-18
申请号：US13531827
申请日：2012-06-25
申请人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Hinmeng Au , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
发明人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Hinmeng Au , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
IPC分类号： H01L25/07 , H01L21/60 , H01L23/538
CPC分类号： H01L23/5385 , H01L21/6835 , H01L23/13 , H01L24/14 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32245 , H01L2224/45099 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73253 , H01L2224/81001 , H01L2224/81005 , H01L2224/81801 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12042 , H01L2924/1461 , H01L2924/15153 , H01L2924/19107 , H01L2924/351 , H01L2924/00
摘要： A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
摘要翻译：多芯片封装包括具有第一侧面（111），相对的第二侧面（112）和从第一侧向第二侧延伸的第三侧面（213）的基板（110），第一模具（120））和附接到所述基板的第一侧的第二模具（130），以及邻近所述基板的第三侧并连接到所述第一模具和所述第二模具的桥接件（140）。基板的任何部分都不在桥下。该桥在第一管芯和第二管芯之间形成连接。或者，桥可以设置在衬底中的空腔（615,915）中，或者设置在衬底和裸片层（750）之间。该桥可以构成一个有源管芯，并且可以使用引线键连接到衬底（241,841,1141,1541）。

9. 发明授权

US09875969B2 Multi-chip package and method of providing die-to-die interconnects in same 有权
公开(公告)号：US09875969B2
公开(公告)日：2018-01-23
申请号：US13531827
申请日：2012-06-25
申请人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
发明人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
IPC分类号： H01L23/12 , H01L23/538 , H01L23/13 , H01L23/00 , H01L25/065 , H01L21/683
CPC分类号： H01L23/5385 , H01L21/6835 , H01L23/13 , H01L24/14 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32245 , H01L2224/45099 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73253 , H01L2224/81001 , H01L2224/81005 , H01L2224/81801 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12042 , H01L2924/1461 , H01L2924/15153 , H01L2924/19107 , H01L2924/351 , H01L2924/00
摘要： A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

10. 发明授权

US08227904B2 Multi-chip package and method of providing die-to-die interconnects in same 有权
标题翻译：多芯片封装和提供芯片间裸片互连的方法
公开(公告)号：US08227904B2
公开(公告)日：2012-07-24
申请号：US12459007
申请日：2009-06-24
申请人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Hinmeng Au , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
发明人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Hinmeng Au , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
IPC分类号： H01L23/538
CPC分类号： H01L23/5385 , H01L21/6835 , H01L23/13 , H01L24/14 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32245 , H01L2224/45099 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73253 , H01L2224/81001 , H01L2224/81005 , H01L2224/81801 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12042 , H01L2924/1461 , H01L2924/15153 , H01L2924/19107 , H01L2924/351 , H01L2924/00
摘要： A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
摘要翻译：多芯片封装包括具有第一侧面（111），相对的第二侧面（112）和从第一侧向第二侧延伸的第三侧面（213）的基板（110），第一模具（120））和附接到所述基板的第一侧的第二模具（130），以及邻近所述基板的第三侧并连接到所述第一模具和所述第二模具的桥接件（140）。基板的任何部分都不在桥下。该桥在第一管芯和第二管芯之间形成连接。或者，桥可以设置在衬底中的空腔（615,915）中，或者设置在衬底和裸片层（750）之间。该桥可以构成一个有源管芯，并且可以使用引线键连接到衬底（241,841,1141,1541）。

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