专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060121653A1 Method for insulating patterns formed in a thin film of oxidizable semi-conducting material 失效
公开(公告)号：US20060121653A1
公开(公告)日：2006-06-08
申请号：US11291918
申请日：2005-12-02
申请人： Maud Vinet , Jean-Charles Barbe , Bernard Previtali , Thierry Poiroux
发明人： Maud Vinet , Jean-Charles Barbe , Bernard Previtali , Thierry Poiroux
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L21/76202
摘要： A method for insulating patterns formed in a thin film made of a first oxidizable semi-conducting material, with a thickness less than or equal to 20 nm and preferably less than or equal to 10 nm, successively comprises: formation, on the thin film, of a mask defining, in the thin film, free zones and zones covered by the mask designed to substantially form the patterns, selective formation, at the level of the free zones of the thin film, of an additional layer formed by an oxide of a second semi-conducting material, oxidization of the free zones of the thin film, removal of the mask so as to release the thin film patterned in the form of patterns insulated by oxidized zones. The first and second semi-conducting materials can be identical and the step of selective formation of the additional layer can be performed by selective epitaxial growth of the free zones of the thin film.

2. 发明授权

US07473588B2 Method for insulating patterns formed in a thin film of oxidizable semi-conducting material 失效
标题翻译：在可氧化半导体材料薄膜中形成绝缘图案的方法
公开(公告)号：US07473588B2
公开(公告)日：2009-01-06
申请号：US11291918
申请日：2005-12-02
申请人： Maud Vinet , Jean-Charles Barbe , Bernard Previtali , Thierry Poiroux
发明人： Maud Vinet , Jean-Charles Barbe , Bernard Previtali , Thierry Poiroux
IPC分类号： H01L21/00
CPC分类号： H01L21/76202
摘要： A method for insulating patterns formed in a thin film made of a first oxidizable semi-conducting material, with a thickness less than or equal to 20 nm and preferably less than or equal to 10 nm, successively comprises: formation, on the thin film, of a mask defining, in the thin film, free zones and zones covered by the mask designed to substantially form the patterns, selective formation, at the level of the free zones of the thin film, of an additional layer formed by an oxide of a second semi-conducting material, oxidization of the free zones of the thin film, removal of the mask so as to release the thin film patterned in the form of patterns insulated by oxidized zones. The first and second semi-conducting materials can be identical and the step of selective formation of the additional layer can be performed by selective epitaxial growth of the free zones of the thin film.
摘要翻译：一种绝缘图案，其形成在厚度小于或等于20nm，优选小于或等于10nm的第一可氧化半导电材料制成的薄膜中，依次包括：在薄膜上形成，在薄膜中限定由掩模覆盖的自由区域和设置成基本上形成图案的区域，在薄膜的自由区域的选择性地形成由氧化物形成的附加层第二半导体材料，氧化薄膜的自由区域，去除掩模，以便释放以氧化区形式绝缘的图案图案化的薄膜。第一和第二半导体材料可以是相同的，并且选择性地形成附加层的步骤可以通过薄膜的自由区域的选择性外延生长来进行。

3. 发明申请

US20110003443A1 METHOD FOR PRODUCING A TRANSISTOR WITH METALLIC SOURCE AND DRAIN 有权
标题翻译：用于生产具有金属源和漏极的晶体管的方法
公开(公告)号：US20110003443A1
公开(公告)日：2011-01-06
申请号：US12796282
申请日：2010-06-08
申请人： Bernard Previtali , Thierry Poiroux , Maud Vinet
发明人： Bernard Previtali , Thierry Poiroux , Maud Vinet
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78648 , H01L29/78696 , Y10S438/924
摘要： A method for producing a transistor with metallic source and drain including the steps of: a) producing a gate stack, b) producing two portions of a material capable of being selectively etched relative to a second dielectric material and arranged at the locations of the source and of the drain of the transistor, c) producing a second dielectric material-based layer covering the stack and the two portions of material, d) producing two holes in the second dielectric material-based layer forming accesses to the two portions of material, e) etching of said two portions of material, f) depositing a metallic material in the two formed cavities, and also including, between steps a) and b), a step of deposition of a barrier layer on the stack, against the lateral sides of the stack and against the face of the first dielectric material-based layer.
摘要翻译：一种用于制造具有金属源极和漏极的晶体管的方法，包括以下步骤：a）产生栅极堆叠，b）产生能够相对于第二介电材料选择性蚀刻的材料的两部分，并且布置在源极的位置处和晶体管的漏极，c）产生覆盖堆叠和两部分材料的第二介电材料基层，d）在第二介电材料基层中产生形成访问两部分材料的两个孔， e）蚀刻所述两部分材料，f）在两个形成的空腔中沉积金属材料，并且还包括在步骤a）和b）之间，将阻挡层沉积在堆叠上的侧面并且抵靠第一介电材料层的表面。

4. 发明授权

US08021986B2 Method for producing a transistor with metallic source and drain 有权
标题翻译：用于制造具有金属源极和漏极的晶体管的方法
公开(公告)号：US08021986B2
公开(公告)日：2011-09-20
申请号：US12796282
申请日：2010-06-08
申请人： Bernard Previtali , Thierry Poiroux , Maud Vinet
发明人： Bernard Previtali , Thierry Poiroux , Maud Vinet
IPC分类号： H01L21/302
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78648 , H01L29/78696 , Y10S438/924
摘要： A method for producing a transistor with metallic source and drain including the steps of: a) producing a gate stack, b) producing two portions of a material capable of being selectively etched relative to a second dielectric material and arranged at the locations of the source and of the drain of the transistor, c) producing a second dielectric material-based layer covering the stack and the two portions of material, d) producing two holes in the second dielectric material-based layer forming accesses to the two portions of material, e) etching of said two portions of material, f) depositing a metallic material in the two formed cavities, and also including, between steps a) and b), a step of deposition of a barrier layer on the stack, against the lateral sides of the stack and against the face of the first dielectric material-based layer.
摘要翻译：一种用于制造具有金属源极和漏极的晶体管的方法，包括以下步骤：a）产生栅极堆叠，b）产生能够相对于第二介电材料选择性蚀刻的材料的两部分，并且布置在源极的位置处和晶体管的漏极，c）产生覆盖堆叠和两部分材料的第二介电材料基层，d）在第二介电材料基层中产生形成访问两部分材料的两个孔， e）蚀刻所述两部分材料，f）在两个形成的空腔中沉积金属材料，并且还包括在步骤a）和b）之间，将阻挡层沉积在堆叠上的侧面并且抵靠第一介电材料层的表面。

5. 发明申请

US20090286363A1 METHOD FOR MAKING A TRANSISTOR WITH METALLIC SOURCE AND DRAIN 有权
标题翻译：用金属源和漏极制造晶体管的方法
公开(公告)号：US20090286363A1
公开(公告)日：2009-11-19
申请号：US12433209
申请日：2009-04-30
申请人： Maud VINET , Thierry Poiroux , Bernard Previtali
发明人： Maud VINET , Thierry Poiroux , Bernard Previtali
IPC分类号： H01L21/336 , H01L27/12
CPC分类号： H01L29/41783 , H01L21/823814 , H01L29/41766 , H01L29/517 , H01L29/66628 , H01L29/66636 , H01L29/66643 , H01L29/66772 , H01L29/7834 , H01L29/7839 , H01L29/78648
摘要： Method for making a field effect transistor comprising the following steps: a) make a structure on a substrate, comprising a channel, a gate and a hard mask, b) formation of a dielectric completely covering said structure and locations of a source and a drain of the transistor and a peripheral zone, c) in the dielectric portion, make two holes exposing the sidewalls of the channel, d) deposit a first metallic layer on the walls of the holes, e) silicide said sidewalls, f) deposit a second metallic layer on the first metallic layer, forming the source and the drain of the transistor with the previously silicided portions, g) chemical mechanical polishing of the second metallic layer with a stop on the hard mask.
摘要翻译：制造场效应晶体管的方法，包括以下步骤：a）在包括沟道，栅极和硬掩模的衬底上形成结构，b）形成完全覆盖所述结构的电介质和源极和漏极的位置和c）在电介质部分中，形成露出沟道侧壁的两个孔，d）在孔的壁上沉积第一金属层，e）硅化所述侧壁，f）沉积第二个在第一金属层上形成金属层，用先前的硅化部分形成晶体管的源极和漏极，g）在硬掩模上用停止物对第二金属层进行化学机械抛光。

6. 发明授权

US08021934B2 Method for making a transistor with metallic source and drain 有权
标题翻译：制造具有金属源极和漏极的晶体管的方法
公开(公告)号：US08021934B2
公开(公告)日：2011-09-20
申请号：US12433209
申请日：2009-04-30
申请人： Maud Vinet , Thierry Poiroux , Bernard Previtali
发明人： Maud Vinet , Thierry Poiroux , Bernard Previtali
IPC分类号： H01L21/8232
CPC分类号： H01L29/41783 , H01L21/823814 , H01L29/41766 , H01L29/517 , H01L29/66628 , H01L29/66636 , H01L29/66643 , H01L29/66772 , H01L29/7834 , H01L29/7839 , H01L29/78648
摘要： A method including: making a structure on a substrate, said structure comprising at least a portion of a semiconductor material forming a channel of a field effect transistor, a gate located on the channel; forming at least one dielectric portion completely covering said structure and zones of the substrate corresponding to locations of a source and a drain of the field effect transistor; making two holes in the dielectric portion on each side of said structure, such that the locations of the source and the drain form bottom walls of the two holes and sides of the channel are exposed; depositing a first metallic layer on at least the bottom walls of the two holes, at least covering said sides of the channel; and depositing a second metallic layer on the first metallic layer-to form the source and the drain of the field effect transistor.
摘要翻译：一种方法，包括：在衬底上形成结构，所述结构包括形成场效应晶体管的沟道的半导体材料的至少一部分，位于沟道上的栅极; 形成至少一个电介质部分，完全覆盖对应于场效应晶体管的源极和漏极的位置的所述结构和衬底的区域; 在所述结构的每一侧的电介质部分中形成两个孔，使得源和漏极形成两个孔的底壁和通道的侧面的位置被暴露; 在至少两个孔的底壁上沉积第一金属层，至少覆盖通道的所述侧面; 以及在第一金属层上沉积第二金属层，以形成场效应晶体管的源极和漏极。

7. 发明授权

US08232168B2 Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate 有权
标题翻译：制造不对称双栅极晶体管的方法，通过该方法可以在同一衬底上制造不对称和对称双栅极晶体管
公开(公告)号：US08232168B2
公开(公告)日：2012-07-31
申请号：US12521311
申请日：2007-12-28
申请人： Maud Vinet , Olivier Thomas , Olivier Rozeau , Thierry Poiroux
发明人： Maud Vinet , Olivier Thomas , Olivier Rozeau , Thierry Poiroux
IPC分类号： H01L21/336
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L29/78645
摘要： A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.
摘要翻译：一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在至少包括构成为形成双栅极晶体管的第一栅极的第一块的至少一个衬底上形成一个或多个结构，并且至少第二块，其被配置为形成所述双栅极的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与所述半导体区分离并且b）使用相对于第一块选择性的至少一种植入，在所述结构中掺杂至少一个给定结构的第二块中的至少一个或多个半导体区域，所述第二块被硬掩模覆盖，硬掩模的临界尺寸大于第二块的临界尺寸。

8. 发明授权

US08324057B2 Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate 有权
标题翻译：用于制造不对称双栅极晶体管的方法，通过该方法可以在同一衬底上制造不对称和对称双栅极晶体管
公开(公告)号：US08324057B2
公开(公告)日：2012-12-04
申请号：US12521239
申请日：2007-12-28
申请人： Maud Vinet , Olivier Thomas , Olivier Rozeau , Thierry Poiroux
发明人： Maud Vinet , Olivier Thomas , Olivier Rozeau , Thierry Poiroux
IPC分类号： H01L21/336
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L29/78645
摘要： A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate.
摘要翻译：一种在同一衬底上制造具有一个或多个不对称和对称双栅极晶体管的微电子器件的方法。

9. 发明申请

US20100096700A1 METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE 有权
标题翻译：用不对称和对称双栅极晶体管制造不对称双栅极晶体管的方法可以在同一基板上
公开(公告)号：US20100096700A1
公开(公告)日：2010-04-22
申请号：US12521239
申请日：2007-12-28
申请人： Maud Vinet , Olivier Thomas , Olivier Rozeau , Thierry Poiroux
发明人： Maud Vinet , Olivier Thomas , Olivier Rozeau , Thierry Poiroux
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L29/78645
摘要： A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate.
摘要翻译：一种在同一衬底上制造具有一个或多个不对称和对称双栅极晶体管的微电子器件的方法。

10. 发明授权

US07361592B2 Method for producing a component comprising at least one germanium-based element and component obtained by such a method 有权
标题翻译：用于制造包含至少一种基于锗的元素和通过这种方法获得的组分的组分的方法
公开(公告)号：US07361592B2
公开(公告)日：2008-04-22
申请号：US11444423
申请日：2006-06-01
申请人： Yves Morand , Thierry Poiroux , Maud Vinet
发明人： Yves Morand , Thierry Poiroux , Maud Vinet
IPC分类号： H01L21/44
CPC分类号： H01L21/76251
摘要： The method successively comprises production, on a substrate, of a stack of layers comprising at least one first layer made from germanium and silicon compound initially having a germanium concentration comprised between 10% and 50%. The first layer is arranged between second layers having germanium concentrations comprised between 0% and 10%. Then a first zone corresponding to the germanium-based element and having at least a first lateral dimension comprised between 10 nm and 500 nm is delineated by etching in said stack. Then at least lateral thermal oxidization of the first zone is performed so that a silica layer forms on the surface of the first zone and that, in the first layer, a central zone of condensed germanium forms, constituting the germanium-based element.
摘要翻译：该方法依次包括在衬底上生产包括由锗制成的至少一个第一层和最初具有10％至50％的锗浓度的硅化合物的层叠层。第一层布置在锗浓度介于0％和10％之间的第二层之间。然后通过在所述堆叠中的蚀刻来描绘对应于锗基元件并且具有在10nm和500nm之间的至少第一横向尺寸的第一区域。然后，至少进行第一区域的侧向热氧化，使得在第一区域的表面上形成二氧化硅层，并且在第一层中形成构成锗基元素的浓缩锗的中心区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式