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1. 发明授权

US06544872B1 Dopant implantation processing for improved source/drain interface with metal silicides 有权
标题翻译：掺杂剂注入处理，用于改善与金属硅化物的源/漏界面
公开(公告)号：US06544872B1
公开(公告)日：2003-04-08
申请号：US09819598
申请日：2001-03-29
申请人： Matthew S. Buynoski , Qi Xiang , George Jonathan Kluth
发明人： Matthew S. Buynoski , Qi Xiang , George Jonathan Kluth
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/26513 , H01L21/823418 , H01L21/823814
摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices is avoided, or at least substantially reduced, by increasing the dopant implantation energy to position the maximum source/drain dopant concentration depth below rather than above the depth to which silicidation reaction occurs, thereby minimizing the concentration of dopant in the metal silicide. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.
摘要翻译：在用于形成MOS晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度通过增加掺杂剂注入能量来定位，以避免或至少大大减少最大源极/漏极掺杂剂浓度深度低于而不是高于发生硅化反应的深度，从而使金属硅化物中掺杂剂的浓度最小化。本发明特别适用于在掺杂Si的衬底上形成NiSi层。

2. 发明授权

US06451693B1 Double silicide formation in polysicon gate without silicide in source/drain extensions 有权
标题翻译：在源极/漏极延伸部分中没有硅化物的多晶硅栅中形成双重硅化物
公开(公告)号：US06451693B1
公开(公告)日：2002-09-17
申请号：US09679370
申请日：2000-10-05
申请人： Christy Mei-Chu Woo , George Jonathan Kluth , Qi Xiang
发明人： Christy Mei-Chu Woo , George Jonathan Kluth , Qi Xiang
IPC分类号： H01L2144
CPC分类号： H01L29/66613 , H01L21/28518 , H01L29/66507
摘要： A silicide gate contact is formed which is relatively thicker than silicide contacts formed over source/drain regions and shallow junction extensions. A metal layer is first deposited to form silicide over the polysilicon gate and the source/drain extension regions. The silicide is removed from the extension regions, forming shallow junctions, and a layer of silicide remains on the polysilicon gate. A second metal deposition step and silicidation step forms silicide contacts over the source/drain regions and the polysilicon gate. The resulting silicide gate contact is thicker than the resulting silicide contacts over the source/drain regions.
摘要翻译：形成硅化物栅极接触，其比在源极/漏极区域和浅结延伸部分上形成的硅化物触点相对更厚。首先沉积金属层以在多晶硅栅极和源极/漏极延伸区域上形成硅化物。从延伸区域去除硅化物，形成浅结，并且多晶硅栅极上保留一层硅化物。第二金属沉积步骤和硅化步骤在源极/漏极区域和多晶硅栅极之上形成硅化物接触。所得到的硅化物栅极接触比源极/漏极区上的所得硅化物接触厚。

3. 发明授权

US06797602B1 Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts 有权
标题翻译：制造具有过饱和源极/漏极延伸部分和金属硅化物触点的半导体器件的方法
公开(公告)号：US06797602B1
公开(公告)日：2004-09-28
申请号：US10071207
申请日：2002-02-11
申请人： George Jonathan Kluth , Qi Xiang
发明人： George Jonathan Kluth , Qi Xiang
IPC分类号： H01L213205
CPC分类号： H01L29/6653 , H01L21/268 , H01L21/324 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7833 , H01L29/7834
摘要： Semiconductor devices, such as transistors, with a supersaturated concentration of dopant in the source/drain extension and metal silicide contacts enable the production of smaller, higher speed devices. Supersaturated source/drain extensions are subject to dopant diffusion out from the source/drain extension during high temperature metal silicide contact formation. The formation of lower temperature metal silicide contacts, such as nickel silicide contacts, prevents dopant diffusion and maintains the source/drain extensions in a supersaturated state throughout semiconductor device manufacturing.
摘要翻译：在源极/漏极延伸和金属硅化物触点中具有过饱和浓度的掺杂剂的晶体管等半导体器件能够生产更小更高速度的器件。在高温金属硅化物接触形成期间，过饱和源极/漏极延伸部分从源极/漏极延伸部分扩散出来。低温金属硅化物接触（例如硅化镍接触）的形成防止掺杂剂扩散，并且在整个半导体器件制造过程中将源极/漏极延伸部保持在过饱和状态。

4. 发明授权

US06764912B1 Passivation of nitride spacer 有权
标题翻译：氮化物间隔物钝化
公开(公告)号：US06764912B1
公开(公告)日：2004-07-20
申请号：US09919943
申请日：2001-08-02
申请人： John Clayton Foster , Eric N. Paton , Matthew S. Buynoski , Qi Xiang , Paul R. Besser , Paul L. King
发明人： John Clayton Foster , Eric N. Paton , Matthew S. Buynoski , Qi Xiang , Paul R. Besser , Paul L. King
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656
摘要： The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.
摘要翻译：栅电极上的氮化硅间隔物中的金属硅化物的形成导致栅电极与半导体器件的源区和漏区之间的桥接。通过在器件上形成金属硅化物层之前在氮化硅间隔物上形成氧化硅薄层来防止桥接。

5. 发明授权

US06440868B1 Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process 失效
标题翻译：具有CVD非晶硅层的金属栅极和用于CMOS器件的硅化物和用替代栅极工艺制造的方法
公开(公告)号：US06440868B1
公开(公告)日：2002-08-27
申请号：US09691259
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21302
CPC分类号： H01L21/28052 , H01L29/517 , H01L29/66545 , Y10S438/926
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then deposited on the CVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。然后将金属沉积在CVD非晶硅层上。退火工艺在栅极中形成硅化物，其中一层硅残留未反应。由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

6. 发明授权

US06376343B1 Reduction of metal silicide/silicon interface roughness by dopant implantation processing 有权
标题翻译：通过掺杂剂注入处理减少金属硅化物/硅界面粗糙度
公开(公告)号：US06376343B1
公开(公告)日：2002-04-23
申请号：US09812695
申请日：2001-03-21
申请人： Matthew S. Buynoski , Paul R. Besser , Qi Xiang
发明人： Matthew S. Buynoski , Paul R. Besser , Qi Xiang
IPC分类号： H01L21425
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/28518 , H01L21/823814 , H01L29/665
摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.
摘要翻译：避免了由于特定掺杂剂和金属硅化物的不良相容性而形成浅晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度，或至少大大降低通过植入与金属硅化物具有相对良好的相容性的第一（主要）掺杂剂物质，使得其最大浓度在高于发生硅化反应的深度的深度处，并且注入具有相对较差相容性的第二（辅助）掺杂剂种类金属硅化物，其中其最大浓度小于第一（主要）掺杂剂的最大浓度，并且处于低于发生硅化反应的深度的深度。本发明特别适用于在掺杂Si的衬底上形成NiSi层。

7. 发明授权

US06291278B1 Method of forming transistors with self aligned damascene gate contact 有权
标题翻译：用自对准镶嵌门接触形成晶体管的方法
公开(公告)号：US06291278B1
公开(公告)日：2001-09-18
申请号：US09303694
申请日：1999-05-03
申请人： Qi Xiang , Matthew S. Buynoski , Ming-Ren Lin
发明人： Qi Xiang , Matthew S. Buynoski , Ming-Ren Lin
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/823871 , H01L29/66545
摘要： A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.
摘要翻译：制造具有浅源极和漏极延伸的晶体管的方法利用自对准接触。漏极延伸部分通过接触区域和栅极结构之间的开口提供。可以使用高K栅介电材料。可以根据所公开的方法创建P-MOS和N-MOS晶体管。

8. 发明授权

US07105421B1 Silicon on insulator field effect transistor with heterojunction gate 有权
公开(公告)号：US07105421B1
公开(公告)日：2006-09-12
申请号：US10835438
申请日：2004-04-29
申请人： Qi Xiang , Matthew S. Buynoski
发明人： Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L29/432 , H01L29/66772 , H01L29/78645
摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

9. 发明授权

US06784506B2 Silicide process using high K-dielectrics 失效
标题翻译：使用高K电介质的硅化物工艺
公开(公告)号：US06784506B2
公开(公告)日：2004-08-31
申请号：US09939744
申请日：2001-08-28
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2976
CPC分类号： H01L29/4933 , H01L21/28167 , H01L21/28194 , H01L29/517 , H01L29/518 , H01L29/665
摘要： A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.
摘要翻译：通过使用镍作为硅化物的金属成分，在栅电极形成金属硅化物期间防止栅电极的高K电介质层的热分解的方法。

10. 发明授权

US06759308B2 Silicon on insulator field effect transistor with heterojunction gate 有权
标题翻译：具有异质结栅的绝缘体上的场效应晶体管
公开(公告)号：US06759308B2
公开(公告)日：2004-07-06
申请号：US09902429
申请日：2001-07-10
申请人： Qi Xiang , Matthew S. Buynoski
发明人： Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L2130
CPC分类号： H01L29/78696 , H01L29/432 , H01L29/66772 , H01L29/78645
摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.
摘要翻译：在隔离掩埋氧化物层上方的薄硅层中的绝缘体上硅（SOI）衬底上形成场效应晶体管（FET）。沟道区域被轻掺杂第一杂质以增加第一类型的自由载流子导电性。源极区和漏极区是具有第一杂质的重掺杂物。栅极和背栅极沿着沟道区域的侧面定位并且从源极区域延伸并且注入具有大于硅的能隙的第二半导体，并且注入杂质以增加第二类型的自由载流子。

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