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1. 发明授权

US07371684B2 Process for preparing electronics structures using a sacrificial multilayer hardmask scheme 有权
标题翻译：使用牺牲多层硬掩模方案制备电子结构的方法
公开(公告)号：US07371684B2
公开(公告)日：2008-05-13
申请号：US11130078
申请日：2005-05-16
申请人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E. Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Theodorus Eduardus Fransiscus Maria Standaert , Xiao Hu Liu
发明人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E. Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Theodorus Eduardus Fransiscus Maria Standaert , Xiao Hu Liu
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/31144 , H01L21/7682
摘要： A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.
摘要翻译：一种用于制备电子结构的方法包括用牺牲多层硬掩模堆叠涂覆衬底叠层，在涂覆在多层硬掩模堆叠的最上层上的抗蚀剂层中形成图案，将图案转移到硬掩模堆叠中，阻挡一部分图案，然后将图案的未封闭部分转印到基底叠层中。使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速地确定技术公开的主题。提交它的理解是，它不会用于解释或限制所附权利要求的范围或含义。

2. 发明申请

US20080251284A1 Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme 有权
标题翻译：使用牺牲多层硬掩模方案的电子结构
公开(公告)号：US20080251284A1
公开(公告)日：2008-10-16
申请号：US12098895
申请日：2008-04-07
申请人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E. Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Thedorus Eduardus Fransiscus Maria Standaert , Xiao Hu Liu
发明人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E. Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Thedorus Eduardus Fransiscus Maria Standaert , Xiao Hu Liu
IPC分类号： H05K1/16
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/31144 , H01L21/7682
摘要： An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.
摘要翻译：一种电子结构，其包括具有介电层的介质层和介电层上方的介电阻挡层中的至少一个金属互连结构的基板，以及涂覆有自组装层的多层硬掩模堆叠，其中自组装层是纳米尺度和/或微细孔隙的图案，其在介电阻挡层中产生并且进入与金属互连结构相邻的电介质层中，以在其中的介电阻挡层和电介质层中产生列。使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。

3. 发明授权

US06972209B2 Stacked via-stud with improved reliability in copper metallurgy 失效
标题翻译：堆叠通孔，提高了铜冶金的可靠性
公开(公告)号：US06972209B2
公开(公告)日：2005-12-06
申请号：US10306534
申请日：2002-11-27
申请人： Birendra N. Agarwala , Conrad A. Barile , Hormazdyar M. Dalal , Brett H. Engle , Michael Lane , Ernest Levine , Xiao Hu Liu , Vincent McGahay , John F. McGrath , Conal E. Murray , Jawahar P. Nayak , Du B. Nguyen , Hazara S. Rathore , Thomas M. Shaw
发明人： Birendra N. Agarwala , Conrad A. Barile , Hormazdyar M. Dalal , Brett H. Engle , Michael Lane , Ernest Levine , Xiao Hu Liu , Vincent McGahay , John F. McGrath , Conal E. Murray , Jawahar P. Nayak , Du B. Nguyen , Hazara S. Rathore , Thomas M. Shaw
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/00
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76829 , H01L21/76838 , H01L23/5226 , H01L2924/0002 , Y10T428/24917 , H01L2924/00
摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.
摘要翻译：一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织互连级别，从而增加互连级别之间堆叠通孔的灵活性。

4. 发明授权

US08405215B2 Interconnect structure and method for Cu/ultra low k integration 失效
标题翻译： Cu /超低k集成的互连结构和方法
公开(公告)号：US08405215B2
公开(公告)日：2013-03-26
申请号：US12906580
申请日：2010-10-18
申请人： Chih-Chao Yang , Conal E. Murray
发明人： Chih-Chao Yang , Conal E. Murray
IPC分类号： H01L23/52
CPC分类号： H01L21/76808 , H01L21/76805 , H01L21/76814 , H01L21/76835 , H01L21/76843
摘要： A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided.
摘要翻译：提供了一种半导体结构，其包括下互连级，其包括具有嵌入其中的至少一个导电特征的第一介电材料; 位于所述第一电介质材料上的电介质覆盖层以及所述至少一个导电特征的一些但不是全部的部分; 以及包括具有至少一个导电填充通孔的第二介电材料和布置在其中的上覆导电填充线的上部互连水平，其中所述导电填充的通孔与所述第一互连水平的所述至少一个导电特征的暴露表面接触通过锚定区域。此外，本发明结构的导电填充通孔和导电填充线通过单个连续扩散阻挡层与第二介电材料分离。因此，第二电介质材料在与导电填充线相邻的区域中不包括受损区域。还提供了一种形成这种互连结构的方法。

5. 发明申请

US20120298948A1 NANOWIRE FET HAVING INDUCED RADIAL STRAIN 有权
标题翻译：具有诱导径向应变的纳米效应管
公开(公告)号：US20120298948A1
公开(公告)日：2012-11-29
申请号：US13566594
申请日：2012-08-03
申请人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/42392 , H01L29/7845 , H01L29/78696
摘要： An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
摘要翻译：提供了一种中间处理装置，包括连接第一和第二绝缘体上硅（SOI）焊盘的纳米线，包括围绕该纳米线的栅极导体和围绕该栅极导体的多晶硅的栅极以及设置成与该栅极导体反应的硅化物形成金属多晶硅以形成完全硅化（FUSI）材料以在纳米线中诱导径向应变。

6. 发明授权

US08198174B2 Air channel interconnects for 3-D integration 有权
标题翻译：空气通道互连用于3-D集成
公开(公告)号：US08198174B2
公开(公告)日：2012-06-12
申请号：US12536176
申请日：2009-08-05
申请人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
发明人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
IPC分类号： H01L21/44
CPC分类号： H01L23/467 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.
摘要翻译：提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合在其接合界面处的垂直堆叠的晶片的晶片。此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过一个或多个开口以从芯片堆叠结构移除热量。

7. 发明申请

US20110031623A1 INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION 失效
标题翻译： Cu / ULTRA低k积分的互连结构和方法
公开(公告)号：US20110031623A1
公开(公告)日：2011-02-10
申请号：US12906580
申请日：2010-10-18
申请人： Chih-Chao Yang , Conal E. Murray
发明人： Chih-Chao Yang , Conal E. Murray
IPC分类号： H01L23/52
CPC分类号： H01L21/76808 , H01L21/76805 , H01L21/76814 , H01L21/76835 , H01L21/76843
摘要： A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided.
摘要翻译：提供了一种半导体结构，其包括下互连级，其包括具有嵌入其中的至少一个导电特征的第一介电材料; 位于所述第一电介质材料上的电介质覆盖层以及所述至少一个导电特征的一些但不是全部的部分; 以及包括具有至少一个导电填充通孔的第二介电材料和布置在其中的上覆导电填充线的上部互连水平，其中所述导电填充的通孔与所述第一互连水平的所述至少一个导电特征的暴露表面接触通过锚定区域。此外，本发明结构的导电填充通孔和导电填充线通过单个连续扩散阻挡层与第二介电材料分离。因此，第二电介质材料在与导电填充线相邻的区域中不包括受损区域。还提供了一种形成这种互连结构的方法。

8. 发明申请

US20090269929A1 NON-PLASMA CAPPING LAYER FOR INTERCONNECT APPLICATIONS 有权
标题翻译：用于互连应用的非等离子体覆盖层
公开(公告)号：US20090269929A1
公开(公告)日：2009-10-29
申请号：US12108119
申请日：2008-04-23
申请人： Chih-Chao Yang , Conal E. Murray
发明人： Chih-Chao Yang , Conal E. Murray
IPC分类号： H01L21/306 , H01L23/538 , H01L21/311 , H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53238 , H01L21/02074 , H01L21/76834 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an interconnect structure which has a high leakage resistance and substantially no metallic residues and no physical damage present at an interface between the interconnect dielectric and an overlying dielectric capping layer. The interconnect structure of the invention also has an interface between each conductive feature and the overlying dielectric capping layer that is substantially defect-free. The interconnect structure of the invention includes a non-plasma deposited dielectric capping layer which is formed utilizing a process including a thermal and chemical-only pretreatment step that removes surface oxide from atop each of the conductive features as well as metallic residues from atop the interconnect dielectric material. Following this pretreatment step, the dielectric capping layer is deposited.
摘要翻译：本发明提供一种互连结构，其具有高的耐漏电性，并且基本上没有金属残留物，并且在互连电介质和上覆电介质覆盖层之间的界面处不存在物理损伤。本发明的互连结构还具有每个导电特征和基本上无缺陷的上覆电介质覆盖层之间的界面。本发明的互连结构包括非等离子体沉积的介电覆盖层，其使用包括热和仅化学预处理步骤的方法形成，该步骤从每个导电特征顶部以及互连上方的金属残留物去除表面氧化物介电材料。在该预处理步骤之后，沉积介电覆盖层。

9. 发明授权

US08399314B2 p-FET with a strained nanowire channel and embedded SiGe source and drain stressors 有权
标题翻译：具有应变纳米线通道和嵌入式SiGe源极和漏极应力的p-FET
公开(公告)号：US08399314B2
公开(公告)日：2013-03-19
申请号：US12731241
申请日：2010-03-25
申请人： Guy Cohen , Conal E. Murray , Michael J. Rooks
发明人： Guy Cohen , Conal E. Murray , Michael J. Rooks
IPC分类号： H01L29/267 , H01L21/84
CPC分类号： H01L29/78696 , H01L29/0673 , H01L29/42392 , H01L29/7848 , H01L29/785
摘要： Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.
摘要翻译：提供了在纳米级基于沟道的场效应晶体管（FET）中嵌入硅锗（e-SiGe）源极和漏极应力的技术。一方面，制造FET的方法包括以下步骤。提供其上具有电介质的掺杂衬底。在电介质上放置至少一个硅（Si）纳米线。掩模纳米线的一个或多个部分，使纳米线的其它部分暴露出来。外延锗（Ge）生长在纳米线的暴露部分上。外延Ge与纳米线中的Si相互扩散以形成纳米线中嵌入纳米线中的压应变的SiGe区域。掺杂衬底用作FET的栅极，纳米线的掩蔽掉的部分用作FET的沟道，并且嵌入的SiGe区域用作FET的源极和漏极区域。

10. 发明授权

US08212218B2 Dosimeter powered by passive RF absorption 有权
标题翻译：剂量计由被动射频吸收提供动力
公开(公告)号：US08212218B2
公开(公告)日：2012-07-03
申请号：US12627076
申请日：2009-11-30
申请人： Cyril Cabral, Jr. , Michael S. Gordon , Steven J. Koester , Conal E. Murray , Kenneth P. Rodbell , Stephen M. Rossnagel , Robert L. Wisnieff , Jeng-bang Yau
发明人： Cyril Cabral, Jr. , Michael S. Gordon , Steven J. Koester , Conal E. Murray , Kenneth P. Rodbell , Stephen M. Rossnagel , Robert L. Wisnieff , Jeng-bang Yau
IPC分类号： G01T1/02
CPC分类号： G01T1/026
摘要： A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency.
摘要翻译：用于确定辐射量的系统包括配置成接收辐射量的剂量计，该剂量计包括具有谐振频率的电路，使得电路的谐振频率根据剂量计接收的辐射量而改变，剂量计还被配置为吸收电路的谐振频率处的RF能量; 射频（RF）发射器，被配置为以共振频率将所述RF能量传输到所述剂量计; 以及接收器，被配置为基于所吸收的RF能量来确定所述剂量计的谐振频率，其中所述辐射量基于所述谐振频率来确定。

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