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1. 发明申请

US20090200683A1 INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME 审中-公开
标题翻译：具有部分自对准VIAS的互连结构及其生产方法
公开(公告)号：US20090200683A1
公开(公告)日：2009-08-13
申请号：US12030756
申请日：2008-02-13
申请人： Matthew Earl Colburn , Nicholas C. Fuller , Elbert Huang , Satyanarayana V. Nitta
发明人： Matthew Earl Colburn , Nicholas C. Fuller , Elbert Huang , Satyanarayana V. Nitta
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76813
摘要： An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias by depositing an interlayer dielectric layer onto a substrate, depositing at least one hardmask onto the interlayer dielectric layer, lithographically forming a via pattern with elongated via features and lithographically forming a line pattern in either order, then either transferring the line patterns first into the interlayer dielectric layer forming line features or transferring the via pattern first into the interlayer dielectric layer as long as the patterns overlap to forming self aligned via features, depositing conducting metals and filling regions corresponding to the line and via features, and planarizing and removing excess metal from the line and via features.
摘要翻译：具有部分自对准的通孔的互连结构，其中在衬底上具有层间电介质层，其包含至少两条横穿平行于衬底的导电金属线和至少两个与衬底正交的导电金属通孔。一种通过在衬底上沉积层间电介质层来生产自对准通孔的方法，将至少一个硬掩模沉积到层间电介质层上，以光刻方式形成具有细长通孔特征的通孔图案，并以任何顺序光刻形成线图案，然后只要图案重叠以形成自对准的通孔特征，沉积导电金属和对应于该线的通孔特征的填充区域，首先将线图案首先转移到层间介质层形成线的特征中或者将该通孔图案转移到层间电介质层中并且从线和通孔特征平坦化和去除多余的金属。

2. 发明授权

US06334960B1 Step and flash imprint lithography 有权
标题翻译：步进和闪光刻印光刻
公开(公告)号：US06334960B1
公开(公告)日：2002-01-01
申请号：US09266663
申请日：1999-03-11
申请人： Carlton Grant Willson , Matthew Earl Colburn
发明人： Carlton Grant Willson , Matthew Earl Colburn
IPC分类号： B44C122
CPC分类号： B82Y10/00 , B29C43/003 , B29C43/021 , B29C2043/025 , B82Y40/00 , G03F7/0002 , H05K3/061 , Y10S977/887 , Y10S977/897
摘要： A method of forming a relief image in a structure comprising a substrate and a transfer layer formed thereon comprises covering the transfer layer with a polymerizable fluid composition, and then contacting the polymerizable fluid composition with a mold having a relief structure formed therein such that the polymerizable fluid composition fills the relief structure in the mold. The polymerizable fluid composition is subjected to conditions to polymerize polymerizable fluid composition and form a solidified polymeric material therefrom on the transfer layer. The mold is then separated from the solid polymeric material such that a replica of the relief structure in the mold is formed in the solidified polymeric material; and the transfer layer and the solidified polymeric material are subjected to an environment to selectively etch the transfer layer relative to the solidified polymeric material such that a relief image is formed in the transfer layer.
摘要翻译：在包括基板和形成在其上的转印层的结构中形成浮雕图像的方法包括用可聚合流体组合物覆盖转印层，然后使可聚合流体组合物与其中形成有浮雕结构的模具接触，使得可聚合的流体组合物填充模具中的浮雕结构。可聚合流体组合物经受聚合可聚合流体组合物并在转移层上形成固化的聚合物材料的条件。然后将模具与固体聚合物材料分离，使得在固化的聚合物材料中形成模具中的浮雕结构的复制品; 并且转印层和固化的聚合物材料经受环境以相对于固化的聚合物材料选择性地蚀刻转印层，使得在转印层中形成浮雕图像。

3. 发明授权

US07947907B2 Electronics structures using a sacrificial multi-layer hardmask scheme 有权
标题翻译：使用牺牲多层硬掩模方案的电子结构
公开(公告)号：US07947907B2
公开(公告)日：2011-05-24
申请号：US12098895
申请日：2008-04-07
申请人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Thedorus Eduardos Standaert , Xiao Hu Liu
发明人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Thedorus Eduardos Standaert , Xiao Hu Liu
IPC分类号： H05K1/03
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/31144 , H01L21/7682
摘要： An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.
摘要翻译：一种电子结构，其包括具有介电层的介质层和介电层上方的介电阻挡层中的至少一个金属互连结构的基板，以及涂覆有自组装层的多层硬掩模堆叠，其中自组装层是纳米尺度和/或微细孔隙的图案，其在介电阻挡层中产生并且进入与金属互连结构相邻的电介质层中，以在其中的介电阻挡层和电介质层中产生柱。使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。

4. 发明授权

US07863150B2 Method to generate airgaps with a template first scheme and a self aligned blockout mask 有权
标题翻译：使用模板第一方案和自对准遮挡掩码生成气隙的方法
公开(公告)号：US07863150B2
公开(公告)日：2011-01-04
申请号：US11518773
申请日：2006-09-11
申请人： Matthew Earl Colburn , Daniel C. Edelstein , Satya Venkata Nitta , Sampath Purushothaman , Shom Ponth
发明人： Matthew Earl Colburn , Daniel C. Edelstein , Satya Venkata Nitta , Sampath Purushothaman , Shom Ponth
IPC分类号： H01L21/76
CPC分类号： H01L21/7682
摘要： A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.
摘要翻译：在具有转印到电介质层上的图案的电介质层和在图案周围的电介质层上转移的自对准阻挡掩模的衬底上产生气隙的结构和方法。

5. 发明申请

US20080251284A1 Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme 有权
标题翻译：使用牺牲多层硬掩模方案的电子结构
公开(公告)号：US20080251284A1
公开(公告)日：2008-10-16
申请号：US12098895
申请日：2008-04-07
申请人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E. Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Thedorus Eduardus Fransiscus Maria Standaert , Xiao Hu Liu
发明人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E. Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Thedorus Eduardus Fransiscus Maria Standaert , Xiao Hu Liu
IPC分类号： H05K1/16
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/31144 , H01L21/7682
摘要： An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.
摘要翻译：一种电子结构，其包括具有介电层的介质层和介电层上方的介电阻挡层中的至少一个金属互连结构的基板，以及涂覆有自组装层的多层硬掩模堆叠，其中自组装层是纳米尺度和/或微细孔隙的图案，其在介电阻挡层中产生并且进入与金属互连结构相邻的电介质层中，以在其中的介电阻挡层和电介质层中产生列。使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。

6. 发明授权

US06719915B2 Step and flash imprint lithography 有权
标题翻译：步进和闪光刻印光刻
公开(公告)号：US06719915B2
公开(公告)日：2004-04-13
申请号：US09908765
申请日：2001-07-19
申请人： Carlton Grant Willson , Matthew Earl Colburn
发明人： Carlton Grant Willson , Matthew Earl Colburn
IPC分类号： B44C122
CPC分类号： B82Y10/00 , B29C43/003 , B29C43/021 , B29C2043/025 , B82Y40/00 , G03F7/0002 , H05K3/061 , Y10S977/887 , Y10S977/897
摘要： A method of forming a relief image in a structure comprising a substrate and a transfer layer formed thereon comprises covering the transfer layer with a polymerizable fluid composition, and then contacting the polymerizable fluid composition with a mold having a relief structure formed therein such that the polymerizable fluid composition fills the relief structure in the mold. The polymerizable fluid composition is subjected to conditions to polymerize polymerizable fluid composition and form a solidified polymeric material therefrom on the transfer layer. The mold is then separated from the solid polymeric material such that a replica of the relief structure in the mold is formed in the solidified polymeric material; and the transfer layer and the solidified polymeric material are subjected to an environment to selectively etch the transfer layer relative to the solidified polymeric material such that a relief image is formed in the transfer layer.
摘要翻译：在包括基板和形成在其上的转印层的结构中形成浮雕图像的方法包括用可聚合流体组合物覆盖转印层，然后使可聚合流体组合物与其中形成有浮雕结构的模具接触，使得可聚合的流体组合物填充模具中的浮雕结构。可聚合流体组合物经受聚合可聚合流体组合物并在转移层上形成固化的聚合物材料的条件。然后将模具与固体聚合物材料分离，使得在固化的聚合物材料中形成模具中的浮雕结构的复制品; 并且转印层和固化的聚合物材料经受环境以相对于固化的聚合物材料选择性地蚀刻转印层，使得在转印层中形成浮雕图像。

7. 发明申请

US20090093114A1 METHOD OF FORMING A DUAL-DAMASCENE STRUCTURE USING AN UNDERLAYER 审中-公开
标题翻译：使用底层形成双重结构结构的方法
公开(公告)号：US20090093114A1
公开(公告)日：2009-04-09
申请号：US11869043
申请日：2007-10-09
申请人： Sean David Burns , Matthew Earl Colburn , Naftali Eliahu Lustig , David R. Medeiros , Kaushal Patel , Libor Vyklicky
发明人： Sean David Burns , Matthew Earl Colburn , Naftali Eliahu Lustig , David R. Medeiros , Kaushal Patel , Libor Vyklicky
IPC分类号： H01L21/4763
CPC分类号： H01L21/022 , H01L21/31144 , H01L21/312 , H01L21/76808
摘要： A method of forming a dual-damascene wire. The method includes forming a via opening in a dielectric layer, filling the via opening with a polymeric formation including at least about 6% by weight of solids of thermal acid generator; heating the polymeric underlayer to a temperature greater than room temperature but less than about 180° C.; lithographically forming a trench in the dielectric layer and filling the via opening and the trench with an electrical conductor, a top surface of the electrical conductor substantially co-planer with the top surface of the second dielectric capping layer.
摘要翻译：一种形成双镶嵌线的方法。该方法包括在电介质层中形成通孔，通过包含至少约6重量％的热酸发生器固体的聚合物填充通孔开口; 将聚合物底层加热到大于室温但小于约180℃的温度; 在电介质层中光刻地形成沟槽并用电导体填充通孔开口和沟槽，电导体的顶表面与第二电介质覆盖层的顶表面基本共面。

8. 发明授权

US07371684B2 Process for preparing electronics structures using a sacrificial multilayer hardmask scheme 有权
标题翻译：使用牺牲多层硬掩模方案制备电子结构的方法
公开(公告)号：US07371684B2
公开(公告)日：2008-05-13
申请号：US11130078
申请日：2005-05-16
申请人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E. Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Theodorus Eduardus Fransiscus Maria Standaert , Xiao Hu Liu
发明人： Matthew Earl Colburn , Ricardo Alves Donaton , Conal E. Murray , Satyanarayana Venkata Nitta , Sampath Purushothaman , Sujatha Sankaran , Theodorus Eduardus Fransiscus Maria Standaert , Xiao Hu Liu
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/31144 , H01L21/7682
摘要： A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.
摘要翻译：一种用于制备电子结构的方法包括用牺牲多层硬掩模堆叠涂覆衬底叠层，在涂覆在多层硬掩模堆叠的最上层上的抗蚀剂层中形成图案，将图案转移到硬掩模堆叠中，阻挡一部分图案，然后将图案的未封闭部分转印到基底叠层中。使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速地确定技术公开的主题。提交它的理解是，它不会用于解释或限制所附权利要求的范围或含义。

9. 发明授权

US07084479B2 Line level air gaps 失效
公开(公告)号：US07084479B2
公开(公告)日：2006-08-01
申请号：US10731377
申请日：2003-12-08
申请人： Shyng-Tsong Chen , Stefanie Ruth Chiras , Matthew Earl Colburn , Timothy Joseph Dalton , Jeffrey Curtis Hedrick , Elbert Emin Huang , Kaushik Arun Kumar , Michael Wayne Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Venkata Nitta , Sampath Purushothaman , Robert Rosenburg , Christy Sensenich Tyberg , Roy RongQing Yu
发明人： Shyng-Tsong Chen , Stefanie Ruth Chiras , Matthew Earl Colburn , Timothy Joseph Dalton , Jeffrey Curtis Hedrick , Elbert Emin Huang , Kaushik Arun Kumar , Michael Wayne Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Venkata Nitta , Sampath Purushothaman , Robert Rosenburg , Christy Sensenich Tyberg , Roy RongQing Yu
IPC分类号： H01L29/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

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