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    • 3. 发明授权
    • Active interconnects and control points in integrated circuits
    • 集成电路中的有源互连和控制点
    • US07242199B2
    • 2007-07-10
    • US11112795
    • 2005-04-21
    • R. Stanley WilliamsPhilip J KuekesFrederick A. PernerGreg SniderDuncan Stewart
    • R. Stanley WilliamsPhilip J KuekesFrederick A. PernerGreg SniderDuncan Stewart
    • G01R27/08
    • H05K7/1092H01L23/5228H01L2924/0002H01L2924/00
    • In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains.
    • 在本发明的各种实施例中,在集成电路的互连层处引入可调电阻器,以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或者在制造之后配置集成电路。 例如,当诸如晶体管的某些内部组件由于制造缺陷而没有指定的电子特性时,可以使用根据本发明的实施例的集成电路的互连层中包括的可调谐电阻的可变电阻的调整 以调整内部电压和/或电平以便改善有缺陷的部件。 在其他情况下,可调谐电阻器可以用作开关以配置集成电路部件,包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。
    • 4. 发明授权
    • Hierarchical on-chip memory
    • 分层片上存储器
    • US08885422B2
    • 2014-11-11
    • US13256242
    • 2009-06-12
    • Gilberto Medeiros RibeiroR. Stanley WilliamsMatthew D. Pickett
    • Gilberto Medeiros RibeiroR. Stanley WilliamsMatthew D. Pickett
    • G11C7/00G11C5/06G11C5/02
    • G11C5/02G11C5/063G11C2213/71
    • A hierarchical on-chip memory (400) includes an area distributed CMOS layer (310) comprising input/output functionality and volatile memory and via array (325, 330), the area distributed CMOS layer (310) configured to selectively address the via array (325, 330). A crossbar memory (305) overlies the area distributed CMOS layer (310) and includes programmable crosspoint devices (315) which are uniquely accessed through the via array (325, 330). A method for utilizing hierarchical on-chip memory (400) includes storing frequently rewritten data in a volatile memory and storing data which is not frequently rewritten in a non-volatile memory (305), where the volatile memory is contained within an area distributed CMOS layer (310) and the non-volatile memory (305) is formed over and accessed through the area distributed CMOS layer (310).
    • 分层片上存储器(400)包括包括输入/​​输出功能的区域分布式CMOS层(310)和易失性存储器和通孔阵列(325,330),所述区域分布式CMOS层(310)被配置为选择性地寻址通孔阵列 (325,330)。 交叉开关存储器(305)覆盖区域分布式CMOS层(310),并且包括通过通孔阵列(325,330)唯一访问的可编程交叉点设备(315)。 一种用于利用分层片上存储器(400)的方法包括:将经常重写的数据存储在易失性存储器中,并将非频繁重写的数据存储在非易失性存储器(305)中,其中易失性存储器包含在区域分布式CMOS 层(310)和非易失性存储器(305)形成在区域分布式CMOS层(310)上并通过区域分布式CMOS层(310)访问。