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1. 发明授权

US07009280B2 Low-k interlevel dielectric layer (ILD) 失效
标题翻译：低k层间介质层（ILD）
公开(公告)号：US07009280B2
公开(公告)日：2006-03-07
申请号：US10709320
申请日：2004-04-28
申请人： Matthew Angyal , Edward Paul Barth , Sanjit Kumar Das , Charles Robert Davis , Habib Hichri , William Francis Landers , Jia Lee
发明人： Matthew Angyal , Edward Paul Barth , Sanjit Kumar Das , Charles Robert Davis , Habib Hichri , William Francis Landers , Jia Lee
IPC分类号： H01L23/58
CPC分类号： H01L23/53295 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02362 , H01L21/31633 , H01L21/76829 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%–10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.
摘要翻译：层间电介质层（ILD）包括低k电介质层; 以及在压电应力下沉积在电介质层顶上的低k电介质膜。电介质层包括低k材料，例如有机硅玻璃（OSG）或SiCOH材料。电介质膜的厚度为电介质层厚度的2％-10％，与电介质层具有相似的化学成分，但具有与电介质层不同的形态。通过改变用于沉积低k电介质层的工艺，在介电层沉积的结束处或在其附近的压应力下沉积电介质膜。

2. 发明授权

US08288270B2 Enhanced electromigration resistance in TSV structure and design 有权
标题翻译： TSV结构和设计中增强的电迁移阻力
公开(公告)号：US08288270B2
公开(公告)日：2012-10-16
申请号：US13397004
申请日：2012-02-15
申请人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L21/4763
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.
摘要翻译：这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

3. 发明申请

US20120199975A1 ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN 有权
公开(公告)号：US20120199975A1
公开(公告)日：2012-08-09
申请号：US13023743
申请日：2011-02-09
申请人： Mukta G. Farooq , John A. Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G. Farooq , John A. Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

4. 发明授权

US07714452B2 Structure and method for producing multiple size interconnections 失效
标题翻译：用于生产多尺寸互连的结构和方法
公开(公告)号：US07714452B2
公开(公告)日：2010-05-11
申请号：US11847776
申请日：2007-08-30
申请人： Lawrence A. Clevenger , Mukta Ghate Farooq , Louis Lu-Chen Hsu , William Francis Landers , Donna S. Zupanski-Nielson , Carl John Radens , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Mukta Ghate Farooq , Louis Lu-Chen Hsu , William Francis Landers , Donna S. Zupanski-Nielson , Carl John Radens , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L21/44
CPC分类号： H05K3/3436 , H01L23/13 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/49 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/06102 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/49109 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H05K2201/094 , H05K2201/09736 , H05K2201/09845 , Y02P70/613 , H01L2224/29099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.
摘要翻译：一种电结构和方法，包括电和机械地连接到第二衬底的第一衬底。第一基板包括第一导电焊盘和第二导电焊盘。第二基板包括第三导电焊盘，第四导电焊盘和第一导电部件。第四导电焊盘包括与第一导电构件的高度不同的高度。导电构件电连接和机械地连接到第四导电垫。第一焊球将第一导电焊盘连接到第三导电焊盘。第一焊球包括第一直径。第二焊球将第二导电焊盘连接到第一导电构件。第二焊球包括第二直径。第一直径大于所述第二直径。

5. 发明授权

US08386977B2 Circuit design checking for three dimensional chip technology 有权
标题翻译：电路设计检查三维芯片技术
公开(公告)号：US08386977B2
公开(公告)日：2013-02-26
申请号：US13113421
申请日：2011-05-23
申请人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
发明人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081
摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.
摘要翻译：一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。转换电路设计可以通过标准验证检查进行处理。该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。如果相应的设计单元对应于镜像侧，则设计单元被镜像。然后所有镜像单元格以正确的顺序与未设计的设计单元合并。合并设计通过标准验证检查进行处理。该工具还可以为两个相邻的芯片创建终端金属摘要。其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

6. 发明授权

US08367543B2 Structure and method to improve current-carrying capabilities of C4 joints 有权
标题翻译：提高C4接头承载能力的结构和方法
公开(公告)号：US08367543B2
公开(公告)日：2013-02-05
申请号：US11308396
申请日：2006-03-21
申请人： Mukta Ghate Farooq , Jasvir Singh Jaspal , William Francis Landers , Thomas E. Lombardi , Hai Pham Longworth , H. Bernhard Pogge , Roger A. Quon
发明人： Mukta Ghate Farooq , Jasvir Singh Jaspal , William Francis Landers , Thomas E. Lombardi , Hai Pham Longworth , H. Bernhard Pogge , Roger A. Quon
IPC分类号： H01L21/44 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/291 , H01L23/293 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05026 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/00014
摘要： A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.
摘要翻译：一种系统和方法包括在基底上沉积电介质层并在介电层上沉积金属层。该系统和方法还包括在金属层上沉积高温扩散阻挡金属帽。该系统和方法还包括在高温扩散阻挡金属帽和第一电介质层上沉积第二电介质层，并将通孔蚀刻到第二电介质层中，使得暴露高温扩散阻挡金属帽。该系统和方法还包括在通孔中沉积凸块下的冶金，并在凸块下金属层上形成C4球。

7. 发明授权

US08237288B1 Enhanced electromigration resistance in TSV structure and design 有权
公开(公告)号：US08237288B1
公开(公告)日：2012-08-07
申请号：US13023743
申请日：2011-02-09
申请人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

8. 发明申请

US20120304138A1 CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY 有权
标题翻译：电路设计检查三维芯片技术
公开(公告)号：US20120304138A1
公开(公告)日：2012-11-29
申请号：US13113421
申请日：2011-05-23
申请人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
发明人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.
摘要翻译：一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。转换电路设计可以通过标准验证检查进行处理。该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。如果相应的设计单元对应于镜像侧，则设计单元被镜像。然后所有镜像单元格以正确的顺序与未设计的设计单元合并。合并设计通过标准验证检查进行处理。该工具还可以为两个相邻的芯片创建终端金属摘要。其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

9. 发明申请

US20080160752A1 METHOD FOR CHIP TO PACKAGE INTERCONNECT 审中-公开
标题翻译：芯片封装互连的方法
公开(公告)号：US20080160752A1
公开(公告)日：2008-07-03
申请号：US11619384
申请日：2007-01-03
申请人： Lawrence Clevenger , Timothy J. Dalton , Mukta Ghate Farooq , William Francis Landers , Carl Radens , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy J. Dalton , Mukta Ghate Farooq , William Francis Landers , Carl Radens , Chih-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/11428 , H01L2224/1145 , H01L2224/1147 , H01L2224/11616 , H01L2224/1184 , H01L2224/11901 , H01L2224/13007 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04953 , H01L2924/0103 , H01L2224/05099
摘要： A damascene method of forming a C4 element includes forming a last level metal layer on a substrate, forming a TV ILD layer on the last level metal layer, forming a lithographically patterned UBM adhesion layer including one of Ti, TiW, Cr and Cu, forming a mandrel layer over the UBM adhesion layer, lithographically patterning the mandrel layer to form an aperture, depositing a solder layer by one of sputtering, evaporation, physical vapor deposition, solder wave or injection molding in the aperture, planarizing the solder layer by CMP, removing the mandrel layer, reflowing the solder to ball the solder to form a ball interconnect, and joining a second substrate with an I/O pad to the ball interconnect.
摘要翻译：形成C4元件的镶嵌方法包括在基底上形成最后一层金属层，在最后一层金属层上形成TV ILD层，形成包括Ti，TiW，Cr和Cu之一的光刻图案的UBM粘附层，形成在UBM粘合层上方的心轴层，光刻图案化心轴层以形成孔，通过溅射，蒸发，物理气相沉积，焊波或注射成型在孔中沉积焊料层，通过CMP平坦化焊料层，去除心轴层，回流焊料以焊接焊料以形成球互连，并将第二衬底与I / O焊盘接合到球互连。

10. 发明申请

US20120199983A1 ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN 有权
标题翻译： TSV结构和设计中的增强电阻率
公开(公告)号：US20120199983A1
公开(公告)日：2012-08-09
申请号：US13397004
申请日：2012-02-15
申请人： Mukta G. Farooq , John A. Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G. Farooq , John A. Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.
摘要翻译：这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

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