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1. 发明授权

US08473874B1 Method and apparatus for automatically fixing double patterning loop violations 有权
标题翻译：自动固定双重图案化环路违规的方法和装置
公开(公告)号：US08473874B1
公开(公告)日：2013-06-25
申请号：US13215113
申请日：2011-08-22
申请人： Karun Sharma , Min Cao , Roland Ruehl
发明人： Karun Sharma , Min Cao , Roland Ruehl
IPC分类号： G06F17/50 , G03F1/00 , G21K5/00
CPC分类号： G06F17/5081 , G03F1/00 , G03F7/70433 , G03F7/70466 , G21K5/00
摘要： A method for automatically generating and prioritizing several design solutions that resolve a double patterning (DP) loop violation in an IC design layout. The method of some embodiments receives a DP loop violation marker and identifies pairs of edges of shapes that form a double patterning loop based on the DP loop violation marker. For each pair of edges that violates the design rule, the method generates one or more design solutions. Each design solution moves a single edge or both edges to resolve the violation. The method of some embodiments computes the cost of applying each design solution to the IC design layout and prioritizes the generated solutions for all the identified pairs of edges based on the computed cost for each solution. The method in some embodiments then selects a solution from the prioritized solutions and applies the selected solution to the design layout.
摘要翻译：一种用于自动生成和优先排列多个设计解决方案的方法，以解决IC设计布局中的双重图案化（DP）循环违规。一些实施例的方法接收DP循环违规标记，并基于DP循环违规标记识别形成双重图案化环路的形状边缘对。对于违反设计规则的每对边缘，该方法生成一个或多个设计解决方案。每个设计解决方案都会移动单个边缘或两个边缘来解决违规。一些实施例的方法计算将每个设计解决方案应用于IC设计布局的成本，并且基于每个解决方案的计算成本来为所有所识别的边对对应生成的解决方案的优先级。一些实施例中的方法随后从优先解决的解决方案中选择解决方案，并将所选择的解决方案应用于设计布局。

2. 发明申请

US20120124536A1 METHOD AND SYSTEM FOR AUTOMATIC GENERATION OF SOLUTIONS FOR CIRCUIT DESIGN RULE VIOLATIONS 有权
标题翻译：自动生成电路设计规则解决方案的方法和系统
公开(公告)号：US20120124536A1
公开(公告)日：2012-05-17
申请号：US12948755
申请日：2010-11-17
申请人： Karun Sharma
发明人： Karun Sharma
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F7/70433 , G03F7/70466 , G06F17/5068 , G06F2217/12
摘要： Some embodiments provide a method for automatically generating several design solutions that remedy a design rule violation committed by a set of shapes in an IC design layout. The method receives a marker that indicates the design rule violation and contains information about the violation. The marker in some embodiments can be rendered as a geometric shape in the IC design layout. Based on the marker, the method generates several solutions each of which will cause the set of shapes to meet the design rule when the solution is applied to the set. Each solution requires moving at least one edge of a shape in the set of shapes.
摘要翻译：一些实施例提供了一种用于自动生成多个设计解决方案的方法，所述设计解决方案补救了IC设计布局中由一组形状提交的设计规则违规。该方法接收一个指示违反设计规则的标记，并包含有关违规的信息。一些实施例中的标记可以在IC设计布局中呈现为几何形状。基于标记，该方法生成几个解决方案，每个解决方案将使该组形状满足设计规则时，该解决方案应用于该集合。每个解决方案需要移动该组形状中的形状的至少一个边缘。

3. 发明授权

US09256708B2 Method and system for automatic generation of solutions for circuit design rule violations 有权
标题翻译：自动生成电路设计规则违规解决方案和系统
公开(公告)号：US09256708B2
公开(公告)日：2016-02-09
申请号：US12948755
申请日：2010-11-17
申请人： Karun Sharma
发明人： Karun Sharma
IPC分类号： G06F17/50 , G03F7/20
CPC分类号： G06F17/5081 , G03F7/70433 , G03F7/70466 , G06F17/5068 , G06F2217/12
摘要： Some embodiments provide a method for automatically generating several design solutions that remedy a design rule violation committed by a set of shapes in an IC design layout. The method receives a marker that indicates the design rule violation and contains information about the violation. The marker in some embodiments can be rendered as a geometric shape in the IC design layout. Based on the marker, the method generates several solutions each of which will cause the set of shapes to meet the design rule when the solution is applied to the set. Each solution requires moving at least one edge of a shape in the set of shapes.
摘要翻译：一些实施例提供了一种用于自动生成多个设计解决方案的方法，所述设计解决方案补救了IC设计布局中由一组形状提交的设计规则违规。该方法接收一个指示违反设计规则的标记，并包含有关违规的信息。一些实施例中的标记可以在IC设计布局中呈现为几何形状。基于标记，该方法生成几个解决方案，每个解决方案将使该组形状满足设计规则时，该解决方案应用于该集合。每个解决方案需要移动该组形状中的形状的至少一个边缘。

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