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    • 1. 发明授权
    • Led array, and led printer head
    • LED阵列和led打印头
    • US06388696B1
    • 2002-05-14
    • US09084324
    • 1998-05-27
    • Masumi TaninakaMitsuhiko OgiharaHiroshi HamanoTakatoku Shimizu
    • Masumi TaninakaMitsuhiko OgiharaHiroshi HamanoTakatoku Shimizu
    • B41J245
    • B41J2/45H01L24/06H01L27/153H01L2224/04042H01L2224/0603H01L2224/45144H01L2224/48465H01L2224/49107H01L2224/49109H01L2924/12036H01L2924/12041H01L2924/00
    • According to the present invention, a plurality of p-type semiconductor layers 13 are formed in a single row and a first layer insulating film 12 having first opening portions 16a and an n-side opening portion 17 is formed on the layers in an n-type semiconductor block 11. On the first layer insulating film 12, p-side electrodes 14 to connect to the p-type semiconductor layers 13 at the first opening portions 16a and an n-side electrode 55 (an n-side contact electrode 55a and an n-side pad electrode 55b) to connect with the n-type semiconductor block 11 at the n-side opening portion 17 are formed. Furthermore, p-side common wirings 4 to connect with specific p-side electrodes 14 are formed via a second layer insulating film 18. The p-side electrodes 14 and the n-side electrode 55 are formed using the same conductive film material through a single film formation and patterning process. An Au alloy film, for instance, may be used to form the conductive film that is to constitute the p-side electrodes 14 and the n-side electrode 55.
    • 根据本发明,多个p型半导体层13形成为单列,并且在n型层中的层上形成具有第一开口部分16a和n侧开口部分17的第一层绝缘膜12, 在第一层绝缘膜12上,在第一开口部16a和n侧电极55(n侧接触电极55a和n侧电极55)连接到p型半导体层13的p侧电极14 形成与n侧开口部17处的n型半导体块11连接的n侧焊盘电极55b)。 此外,通过第二层绝缘膜18形成与特定p侧电极14连接的p侧公共配线4.P侧电极14和n侧电极55使用相同的导电膜材料通过 单膜形成和图案化工艺。 例如,可以使用Au合金膜来形成构成p侧电极14和n侧电极55的导电膜。
    • 2. 发明授权
    • LED array
    • LED阵列
    • US06211537B1
    • 2001-04-03
    • US09040450
    • 1998-03-18
    • Takatoku ShimizuMitsuhiko OgiharaMasumi TaninakaHiroshi Hamano
    • Takatoku ShimizuMitsuhiko OgiharaMasumi TaninakaHiroshi Hamano
    • H01L3300
    • B41J2/45H01L27/153H01L33/0008
    • A 1200 dpi LED may be manufactured without highly accurate mask alignment and provide good light radiation efficiency. A first interlayer dielectric is formed on a semiconductor substrate and has a plurality of first windows formed therein and aligned in a row. A diffusion region is formed in the semiconductor substrate through each of the first windows. An electrode is formed to have an area in contact with the corresponding diffusion region. Another electrode is formed on the other side of the substrate. A second interlayer dielectric is formed on the first interlayer dielectric such that the second interlayer dielectric does not overlap the area of the electrode and does not extend to a first perimeter of the area.
    • 可以在没有高精度掩模对准的情况下制造1200dpi的LED,并提供良好的光辐射效率。 第一层间电介质形成在半导体衬底上,并且具有形成在其中的多个第一窗口并排成一行。 通过每个第一窗口在半导体衬底中形成扩散区域。 电极形成为具有与相应的扩散区域接触的区域。 另一电极形成在基板的另一侧。 第二层间电介质形成在第一层间电介质上,使得第二层间电介质不与电极的区域重叠,并且不延伸到该区域的第一周边。
    • 4. 发明授权
    • Method of manufacturing light-receiving/emitting diode array chip
    • 制造光接收/发光二极管阵列芯片的方法
    • US5972729A
    • 1999-10-26
    • US31534
    • 1998-02-27
    • Takatoku ShimizuMitsuhiko OgiharaMasumi TaninakaHiroshi Hamano
    • Takatoku ShimizuMitsuhiko OgiharaMasumi TaninakaHiroshi Hamano
    • B41J2/44B41J2/45B41J2/455H01L21/301H01L27/15H01L31/10H01L33/08H01L33/30H01L33/44H01L33/48H01L33/00
    • H01L27/153B41J2/45H01L33/0008Y10S438/975
    • A method of manufacturing a light-emitting or a light-receiving diode array chip. A first interlayer dielectric is formed in each of a plurality of chip areas on a substrate of a first conductivity type. Impurity diffusion regions of a second conductivity type are formed in the substrate using the first interlayer dielectric as a diffusion mask. An electrode is formed in contact with each of the impurity diffusion regions. The substrate is separated so that the plurality of chip areas are separated into individual chips. A second interlayer dielectric may be formed on the first interlayer dielectric after forming the impurity diffusion regions. The second interlayer dielectric is formed such that the second interlayer dielectric is absent from a second area along which the substrate is separated into the individual chips, at least in the vicinity of the last one of a plurality of windows. Island-shaped patterns may be formed on the interlayer dielectric so as to hold the interlayer dielectric onto the substrate. The first interlayer dielectric may be removed such that the first interlayer dielectric is absent from the second area, at least in the vicinity of the last one of the plurality of windows.
    • 一种制造发光或光接收二极管阵列芯片的方法。 在第一导电类型的衬底上的多个芯片区域中的每一个中形成第一层间电介质。 使用第一层间电介质作为扩散掩模,在衬底中形成第二导电类型的杂质扩散区域。 形成与每个杂质扩散区接触的电极。 分离基板使得多个芯片区域分离为单独的芯片。 在形成杂质扩散区之后,可以在第一层间电介质上形成第二层间电介质。 第二层间电介质形成为使得第二层间电介质不存在于第二区域中,至少在多个窗口中的最后一个窗口附近,基板沿着该第二区域分离成单独的芯片。 可以在层间电介质上形成岛状图案,以将层间电介质保持在基板上。 可以去除第一层间电介质,使得至少在多个窗口中的最后一个窗口附近,第二区域中不存在第一层间电介质。
    • 7. 发明授权
    • Light emitting semiconductor device
    • 发光半导体器件
    • US06762437B2
    • 2004-07-13
    • US10322740
    • 2002-12-19
    • Mitsuhiko OgiharaHiroshi HamanoMasumi Taninaka
    • Mitsuhiko OgiharaHiroshi HamanoMasumi Taninaka
    • H01L3300
    • H01L33/14B41J2/45H01L27/153
    • A light emitting semiconductor device comprises an upper cladding layer (106) consisting of a first upper cladding layer (106a) provided on an active layer (105) and a second upper cladding layer (106b) provided on the first upper cladding layer (106a) to increase the light emitting efficiency and reduce the defective ratio in formation of a patterned layer. The energy band gap (Eg(106a)) of the first upper cladding layer (106a) is larger than the energy band gap (Eg(106b)) of the second upper cladding layer (106b), which is larger than the energy band gap (Eg(105)) of the active layer (105). One of a patterned layer, an dielectric interlayer (109) has an etched region at a predetermined area thereof so that at least a part of the upper cladding layer (106) or a second conductive type semiconductor region (108) is exposed.
    • 一种发光半导体器件包括由设置在有源层(105)上的第一上包层(106a)和设置在第一上包层(106a)上的第二上包层(106b)组成的上包层(106) 以增加发光效率并降低形成图案层的缺陷率。 第一上包层(106a)的能带隙(Eg(106a))大于第二上包层(106b)的能带隙(Eg(106b)),其大于能带隙 (Eg(105))。 图案层之一,电介质中间层(109)在其预定区域具有蚀刻区域,使得上覆层(106)或第二导电类型半导体区域(108)的至少一部分露出。