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1. 发明授权

US5432783A System and method for providing egress policing for broadband virtual private networks 失效
标题翻译：为宽带虚拟专用网提供出口监管的系统和方法
公开(公告)号：US5432783A
公开(公告)日：1995-07-11
申请号：US192764
申请日：1994-02-07
申请人： Masuma Ahmed , Douglas P. Clark , Shin-ichiro Hayano
发明人： Masuma Ahmed , Douglas P. Clark , Shin-ichiro Hayano
IPC分类号： H04Q3/00 , H04L12/56 , H04Q11/04 , H04J3/24
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5615 , H04L2012/5636 , H04L2012/5672
摘要： A system and method for operating a Broadband ISDN to support a viable virtual private network (VPN) service are attained by establishing a plurality of virtual path links connecting customer locations and broadband switching systems, by cross-connecting virtual channel links at the broadband switching systems to establish end-to-end virtual channel connections, and by policing both the input and output traffic only on the virtual path links. The egress policing function is attained through the use of the ingress policing processors by looping back one customer's traffic from an outgoing trunk into an input port on the broadband switching system.
摘要翻译：用于操作宽带ISDN以支持可行的虚拟专用网（VPN）服务的系统和方法通过在宽带交换系统上交叉连接虚拟信道链路来建立连接客户位置和宽带交换系统的多个虚拟路径链路来实现建立端到端的虚拟通道连接，并且仅在虚拟路径链路上监视输入和输出流量。通过使用入口监管处理器，将一个客户的流量从出口中继回送到宽带交换系统的输入端口，可以实现出口监管功能。

2. 发明授权

US4941141A Time division switching for multi-channel calls using two time switch memories acting as a frame aligner 失效
标题翻译：使用两个作为帧对准器的时间开关存储器进行多通道呼叫的时分切换
公开(公告)号：US4941141A
公开(公告)日：1990-07-10
申请号：US291673
申请日：1988-12-29
申请人： Shin-ichiro Hayano
发明人： Shin-ichiro Hayano
IPC分类号： H04J3/06 , H04Q11/08
CPC分类号： H04J3/0629 , H04Q11/08
摘要： Signals on an incoming highway of a time division switching system are written into an alternate one of first and second time switch memories and are sequentially read out of the other alternate one of the memories into the time slots of an outgoing highway of the system in accordance with a phase difference between incoming and outgoing frames and a time slot interchanging relationship between signals on the incoming highway and corresponding signals on the outgoing highway, so that the beginning of the outgoing frame coincides with one of the time slots of the incoming frame which is displaced from the beginning of the incoming frame by an amount equal to the detected phase difference. Alternatively, if the time slot of at least one signal of a multi-channel call on the incoming highway is later than the time slot of a corresponding signal on the outgoing highway, all signals of that multi-channel call are sequentially read out of the memories into a given outgoing highway so that they correspond to those on an incoming frame which is one frame prior to the one being written at the beginning of the given outgoing frame. If the time slots of all signals of a multi-channel call on the incoming highway are earlier than those of respectively corresponding signals on the outgoing highway, all signals of that multi-channel call are sequentially read out of the memories into an outgoing frame so that they correspond to those on an incoming frame which is being written at the beginning of the outgoing frame.

3. 发明授权

US4835770A Multiplexer/demultiplexer circuitry for LSI implementation 失效
标题翻译：用于LSI实现的多路复用器/解复用器电路
公开(公告)号：US4835770A
公开(公告)日：1989-05-30
申请号：US101952
申请日：1987-09-28
申请人： Shin-ichiro Hayano
发明人： Shin-ichiro Hayano
IPC分类号： H04J3/06 , H04Q11/06
CPC分类号： H04J3/0605 , H04Q11/06
摘要： A multiplexer/demultiplexer comprises a code pattern generator for generating a series of unique code patterns at periodic intervals, a plurality of multiplexers cascaded from the code pattern generator to one end of a channel. Each of the multiplexers includes a synchronizer for detecting a particular one of the unique code patterns and a slot selector for multiplexing input data packets into time slots uniquely identified by the particular code pattern to form a data bit stream with the code patterns which is forwarded to the channel. A plurality of demultiplexers are connected to the opposite end of the channel, each of the demultiplexers comprising a synchronizer for detecting a particular one of the code patterns from the data bit stream and a gate for extracting data packets from the time slots uniquely identified by the detected code pattern.
摘要翻译：多路复用器/解复用器包括用于以周期性间隔产生一系列唯一码模式的码模式发生器，从码模式发生器级联到信道一端的多路复用器。每个多路复用器包括用于检测特定代码模式中的特定一个的同步器和用于将输入数据分组复用到由特定代码模式唯一标识的时隙中的时隙选择器，以形成具有被转发到的代码模式的数据比特流这个频道。多个解复用器连接到信道的相对端，每个解复用器包括用于从数据比特流检测码模式中的特定一个的同步器和用于从由数据比特流唯一标识的时隙中提取数据分组的门检测到代码模式。

4. 发明授权

US5132966A Call control with transmission priority in a packet communication network of an ATM type 失效
标题翻译：在ATM类型的分组通信网络中具有传输优先级的呼叫控制
公开(公告)号：US5132966A
公开(公告)日：1992-07-21
申请号：US496973
申请日：1990-03-23
申请人： Shin-ichiro Hayano , Hiroshi Suzuki
发明人： Shin-ichiro Hayano , Hiroshi Suzuki
IPC分类号： H04L12/54 , H04L12/70
CPC分类号： H04L12/5602 , H04L2012/5632 , H04L2012/5651
摘要： In a high-speed packet multiplex communication network including a transmission line with a predetermined bandwidth and accommodating a plurality of information sources, the sources having various packet delivery rates over a range of between a peak rate and a lower rate than an average rate and demanding various transport performances, the sources are preliminarily classified into a plurality of types according to transport performances required and different transmission priorities are assigned to the different types, respectively. Bandwidths of sources of first priority and second priority are determined ones corresponding to the peak rate and the average rate, respectively. A virtual bandwidth may be calculated for the second priority source as a value between the peak and average rates. In response to connection requests from the sources, each of the connection requests is admitted when a bandwidth defined by the priority of each source is accepted in a residual bandwidth of the predetermined bandwidth, and the packets from the source of the first priority are preferentially transmitted to the transmission line, packets of the second priority source are transmitted when packets of the first priority source are absent. Thus, high bandwidth efficiency is insured while the high transport performance of the first priority source is maintained.

5. 发明授权

US4749954A Current switch capable of producing a stable output of a desired level 失效
标题翻译：电流开关能够产生所需电平的稳定输出
公开(公告)号：US4749954A
公开(公告)日：1988-06-07
申请号：US60858
申请日：1987-06-12
申请人： Shin-ichiro Hayano
发明人： Shin-ichiro Hayano
IPC分类号： H03K17/687 , H03K17/693 , H03F3/45
CPC分类号： H03K17/693
摘要： A current switch is disclosed. The current switch comprises an arrangement for converting the difference between input signals fed to first and second input terminals into the difference between output signals from first and second output terminals; a power source for supplying a constant current to the converting arrangement; constant voltage means connected between a first output terminal of the converting arrangement and the power source; a first resistor, one end of which is connected to the power source; a second resistor, one end of which is connected to the other end of the first resistor and the other end of which is connected to the first output terminal of the converting arrangement; and a third resistor, one end of which is connected to the other end of the first resistor and the other end of which is connected to the second output terminal of the converting arrangement, wherein an output signal is taken out of the second output terminal.
摘要翻译：公开了电流开关。电流开关包括用于将馈送到第一和第二输入端的输入信号之间的差转换成来自第一和第二输出端的输出信号之间的差的装置; 用于向转换装置提供恒定电流的电源; 连接在转换装置的第一输出端子和电源之间的恒压装置; 第一电阻器，其一端连接到电源; 第二电阻器，其一端连接到第一电阻器的另一端，另一端连接到转换装置的第一输出端子; 以及第三电阻器，其一端连接到第一电阻器的另一端并且另一端连接到转换装置的第二输出端子，其中输出信号从第二输出端子中取出。

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