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1. 发明授权

US06271567B1 Belowground and oversupply protection of junction isolated integrated circuits 有权
标题翻译：接地隔离集成电路的地下和过充保护
公开(公告)号：US06271567B1
公开(公告)日：2001-08-07
申请号：US09227946
申请日：1999-01-11
申请人： Massimo Pozzoni , Paolo Cordini , Domenico Rossi , Giorgio Pedrazzini , Paola Galbiati , Michele Palmieri , Luca Bertolini
发明人： Massimo Pozzoni , Paolo Cordini , Domenico Rossi , Giorgio Pedrazzini , Paola Galbiati , Michele Palmieri , Luca Bertolini
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.
摘要翻译：在包括功率DMOS晶体管的结隔离集成电路中，形成在相应的阱区域中或者在相反导电类型的衬底上的隔离的外延区域中形成的电路形成在对供过剩和/或地下效应敏感的不同隔离区域中。这些影响是由耦合到电源轨或地的各个功率DMOS晶体管引起的。这些效果可以通过特定形状的布置布置来替代地控制，并且可以被有效地保护免受两种影响。这通过介于敏感电路的区域和包含不形成替代可实施的电路布置的功率DMOS晶体管的区域来实现，该区域包含耦合到电源轨的功率DMOS晶体管或接地导轨，可替代地实施的布置形成。特殊插件将灵敏电路与供电或地下效应不受特定电路布置的电源设备分离和屏蔽。

2. 发明授权

US5565806A Input/output interface circuit for digital and/or analog signals 失效
标题翻译：用于数字和/或模拟信号的输入/输出接口电路
公开(公告)号：US5565806A
公开(公告)日：1996-10-15
申请号：US262590
申请日：1994-06-20
申请人： Paolo Cordini , Giorgio Pedrazzini , Domenico Rossi
发明人： Paolo Cordini , Giorgio Pedrazzini , Domenico Rossi
IPC分类号： H03K19/018 , G06J1/00 , H03F3/62 , H03F3/68 , H03B1/00
CPC分类号： H03F3/62 , G06J1/00
摘要： The present invention relates to an integrated input/output interface for low and/or high voltage range signals of the digital and/or analog type. It comprises essentially a power amplification circuit block (2) having at least one low voltage range input terminal (A) and at least one high voltage range output terminal (B), and a second amplification circuit block (3) having a high voltage range input terminal connected to said high voltage range output terminal (B) and at least one low voltage range output terminal (D). A conventional circuit block (4) prevents a high voltage range signal being input to said high voltage range terminal (B) from propagating through the first power amplification circuit block (2), so that it only affects the second amplification circuit block (3). This interface is implemented in mixed high voltage bipolar/CMOS/DMOS technology.
摘要翻译：本发明涉及用于数字和/或模拟类型的低和/或高电压范围信号的集成输入/输出接口。它基本上包括具有至少一个低电压范围输入端（A）和至少一个高电压范围输出端（B）的功率放大电路块（2）和具有高电压范围的第二放大电路块（3）输入端子连接到所述高压范围输出端子（B）和至少一个低电压范围输出端子（D）。常规电路块（4）防止输入到所述高电压范围端子（B）的高电压范围信号传播通过第一功率放大电路块（2），从而仅影响第二放大电路块（3）。该接口采用混合高压双极/ CMOS / DMOS技术实现。

3. 发明授权

US5629610A Dual threshold current mode digital PWM controller 失效
标题翻译：双阈值电流模式数字PWM控制器
公开(公告)号：US5629610A
公开(公告)日：1997-05-13
申请号：US436947
申请日：1995-05-08
申请人： Giorgio Pedrazzini , Giuseppe Scrocchi , Paolo Cordini , Domenico Rossi
发明人： Giorgio Pedrazzini , Giuseppe Scrocchi , Paolo Cordini , Domenico Rossi
IPC分类号： G05F1/56 , H02M1/08 , H02M3/155 , H02M3/156 , G05F1/563
CPC分类号： H02M3/156 , H02M3/1563
摘要： A fully digital, current mode, PWM control is realized by employing two distinct comparators, both reading the voltage drop on a sensing resistance. The first comparator exerts an open-loop current mode control. The second comparator, establishing a second higher current threshold than the current threshold set by the first comparator, triggers a disabling circuit of the output power transistor for a preset period of time, when the current level through the output stage uncontrollably rises beyond the second threshold. This may occur because of an insufficient discharge from the load circuit inductance during off-phases of the output power transistor of the extra energy stored during switching delay periods of the first (open loop control) comparator. The frequency of the sequence of bursts may be precisely controlled to be well outside the frequency range of interest to prevent disturbances.
摘要翻译：全数字电流模式通过采用两个不同的比较器来实现PWM控制，这两个比较器都读取感测电阻上的电压降。第一个比较器进行开环电流模式控制。第二比较器建立比由第一比较器设置的电流阈值更高的第二高电流阈值，在通过输出级的电流电平不可控地超过第二阈值时，触发输出功率晶体管的禁用电路达预设时间段。这可能是因为在第一（开环控制）比较器的开关延迟时段期间存储的额外能量的输出功率晶体管的非相位期间来自负载电路电感的不充分的放电。突发序列的频率可以被精确地控制在很好的在感兴趣的频率范围之外，以防止干扰。

4. 发明授权

US5483189A Input/output adapted to operate with low and high voltages 失效
标题翻译：输入/输出适用于低压和高压工作
公开(公告)号：US5483189A
公开(公告)日：1996-01-09
申请号：US332831
申请日：1994-10-31
申请人： Paolo Cordini , Giorgio Pedrazzini , Domenico Rossi
发明人： Paolo Cordini , Giorgio Pedrazzini , Domenico Rossi
IPC分类号： H03K19/0175 , H03K5/153
CPC分类号： H03K19/017563 , H03K19/01759
摘要： A stage of both input and output configurable for operation with low and high voltages, comprises:first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, the first terminal of the second transistor (M2), and a drive circuit means, the second terminal and control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to the drive circuit means, the first and second terminals and control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, the circuit node (A), and the drive circuit means;at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); andan input circuit (3) having a first input terminal connected to the circuit node (A), a second input terminal connected to a reference voltage (Vref3), and at least one output terminal forming an output terminal of the stage (I).
摘要翻译：输入和输出可配置为用于低电压和高电压操作的阶段包括：第一（M1），第二（M2）和第三（M3）晶体管，每个具有第一和第二端子以及控制端子，第一和第二端子和第一晶体管（M1）的控制端子分别连接到电压源的第一端子，第二晶体管（M2）的第一端子和驱动电路装置，第二晶体管的第二端子和控制端子 M2）分别连接到电路节点（A），形成载物台（1）的输入/输出端子，分别连接到驱动电路装置，第三晶体管（M3）的第一和第二端子和控制端子分别连接到电压源的第二端子，电路节点（A）和驱动电路装置; 连接在第二晶体管（M2）的第一和第二端子之间的至少一个二极管（D2）; 以及输入电路（3），其具有连接到所述电路节点（A）的第一输入端子，连接到参考电压（Vref3）的第二输入端子和形成所述载物台（I）的输出端子的至少一个输出端子，。

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